Superscalar

For DLX, consider two pipelines, one for integer instructions and one for FP instructions.

Instruction bandwidth is double: each cycle we must fetch 64 bits of instruction
Hazard detection is more complex: we must look for dependencies between the two instructions fetched. The issue logic must decide whether it can issue one or both of the instructions fetched.

Statically schedule code so that instructions fall on a 64 bit boundary with an integer and FP instruction wherever possible.

     Loop:  ld     f0, 0(r1)
            addd   f4, f0, f2
            sd     0(r1), f4
            subi   r1, r1, #8
            bnez   r1, Loop

To effectively make use of the superscalar pipelines without delays, we need to unroll the loop 5 times:

Static

though we can rely on the issue logic to handle stuctural hazards (i.e. we don't need extra nops).

Dynamic

using a variation of the Tomasulo algorithm

Use separate reservation stations/CDB's for integer and FP functional units.
Load/Store reservation stations become load queue
Must disambiquate memory aliases:
- Load checks Store queue to avoid RAW hazards
- Store checks Load queue to avoid WAW and WAR hazards

Iteration	Instruction	Issue	Executes	Write result
1	ld f0,0(r1)	1	2	4
1	addd f4,f0,f2	1	5	8
1	sd 0(r1),f4	2	9
1	subi r1,r1,#8	3	4	5
1	bnez r1, Loop	4	5
2	ld f0,0(r1)	5	6	8
2	addd f4,f0,f2	5	9	12
2	sd 0(r1),f4	6	13
2	subi r1,r1,#8	7	8	9
2	bnez r1, Loop	8	9

to Multiple Issue.