Performance of Multi-Issue Processors

Assumptions

Issue logic may look arbitrarily in the code to find executable instructions.

Branch and jump prediction are perfect

An infinite number of registers for renaming to avoid WAR and WAW hazards

Memory aliases resolved perfectly.

A realizable processor

Up to 64 instruction issues per clock

Selective predictor with 1K entries and a 16 entry return predictor

Perfect memory disambiguation

Register renaming with 64 additional integer and 64 additional FP registers

The PPC 620