The first implementation of the racquetball game is a single
player game for which you will build several of the major modules
for the final game.
The following are descriptions of the Racket Module and Court Display.
Description of Racket Module:
The racket module is shown below
The module has an output "Sw" (for "Swing") and an input "Pl" (for "Player"). The controller can choose the Player it wishes to observe by setting "Pl". If Pl = 0 then the controller chooses to observe Player A, and if Pl = 1 then the controller chooses to observe Player B. The output "Sw" equals 1 if the player chosen has just pushed his/her button (i.e, "swung" his/her racket). Otherwise, "Sw" equals 0.
The Racket Module is actually composed of submodules as shown below.
Note that a circuit called a 2:1 multiplexer (also written as 2-to-1 multiplexer, or 2:1 mux, or 2:1 selector) is used. A description of a generic 2:1 multiplexer is given in the textbook on pp. 181-182. It has three inputs (A, B, Select) and one output Y. (In the textbook, the inputs are (I0, I1, A) and the output is Y.) The inputs A and B are the "data" inputs, and the Select input is the "control." If Select = 0 then Y = A. On the other hand, if Select = 1 then Y = B. A multiplexer is also called a "selector" because it selects which input (A or B) is connected to the output Y.
The multiplexer is to be implemented using the 74157, which is actually a collection of four 2:1 multiplexers with a common Select input. The first multiplexer has inputs (1A,1B) and output 1Y; the second multiplexer has inputs (2A,2B) and output 2Y; the third multiplexer has inputs (3A,3B) and output 3Y; and the fourth multiplexer has inputs (4A, 4B) and output 4Y. See pp. 186-187 of the textbook for a description of the '157 under the subsection "TTL multiplexer components."
The 74157 also has an additional "Strobe" input (or "enable G" input). If the Strobe = H then all outputs (1Y, 2Y, 3Y, 4Y) are L which basically deactivates the multiplexers. If the Strobe = L then the multiplexers are active and perform as follows. If Select = L then 1Y = 1A, 2Y = 2A, 3Y = 3A, and 4Y = 4A. If Select = H then 1Y = 1B, 2Y = 2B, 3Y = 3B, and 4Y = 4B.
The button submodules are connected to the button switches, which are single pole single throw (SPST) switches (see page 151 of the textbook for a review). The submodule outputs are "SwA" and "SwB" for players A and B, respectively. They indicate when a player has "swung" his/her racket. A player "swings" by pushing the button. Note that if the player keeps the button down then that shouldn't correspond to the player continuously "swinging."
The output of a button submodule should have the following timing diagram.
Note that as soon as the switch is depressed (pushed down), the output of the button submodule goes to "1," and then goes to zero after the next upward clock transition. In this way, after the racket is swung, the output is "0."
The button submodule for Player A is organized as follows (the submodule for Player B is identical).
The D flip flop on the left (attached to the SPST switch) is a 7474 device. Actually there are two D flip flops on a 7474 chip. But the D flip flops are different from the ones in a 74175. These flip flops have additional "clear" (CLR) and "preset" (PR) inputs. If the clear is asserted (by a L input) then the output Q goes to 0 immediately, i.e., it's not synchronized with the clock. Similarly, if the preset is asserted then the output Q goes to 1 immediately. These inputs are called "asynchronous" because the output immediately reacts to them.
The way the 7474 D flip flop is set up, when the switch is pressed down, the "clear" input is asserted and the output Q immediately goes to 0. Note that Q will change back to 1 at the next clock transition, because the input D is permanently set to 1.
To complete the design for the button submodule, you must design Module P, which requires at most one D flip flop. For Module P, use a flip flop on a 74175 device.
Task 1.
Draw the ASM chart for Module P. Note that its input is Q (from the '74 D flip flop) and that its output is SwA. Module P should have two states: "Button was not pressed"and "Button was pressed."
Task 2.
Construct the Racket Module in Xilinx. Note that it's composed of two button
submodules and a 2:1 multiplexer. Use the 74157 device for the multiplexer.
Get a print out of your working Xilinx circuit.
Task 3.
Your group should build a working Racket Module circuit on a protoboard. Make sure to convert the circuit diagram into a schematic diagram by including the device numbers and pin numbers for each device.
Description of the Court Display.
The following is a block diagram of the Court Display (the clock input is implied, and not shown in the diagram).
Note that there are six outputs (L1, L2,..., L6) that are connected to LED 1, LED 2,..., LED 6, respectively. Note that they have the negative logic convention. There are two more outputs: Game and HZone. Game = 1 if and only if the ball is in play (i.e., one of the LEDs is ON). HZone = 1 if and only if the ball is returning and is at LED 1. Thus, HZone = 1 means that a player can Hit the ball. There are two inputs: Run and SwC. SwC = 1 means that a player is swinging his/her racket. If the ball is out of play then SwC = 1 will mean that a serve is taking place. Run = 1 will advance the ball in the court display. If Run = 0 then the ball will hold its position. For Racketball I, the input Run should be set to 1. However, for Racketball II, where ball speeds may change, we'll have Run equal 0 and 1 to control the speed.
The display should have the following states:
State Interpretation
S0 Ball is at LED 1 and is proceeding in the direction of the Wall
S1 Ball is at LED 2 " " " " "
S2 Ball is at LED 3 " " " " "
S3 Ball is at LED 4 " " " " "
S4 Ball is at LED 5 " " " " "
S5 Ball is at LED 6 and bounces off the wall
S7 Ball is at LED 5 and is proceeding toward the players
S8 Ball is at LED 4 " " " " "
S9 Ball is at LED 3 " " " " "
S10 Ball is at LED 2 " " " " "
S11 Ball is at LED 1 and is proceeding past the players and is about to go off the court
S12 Ball is out of play
Question 1:
In what state will HZone = 1?
Question 2:
In what state will Game = 0?
Question 3:
Suppose the circuit is in state S12 (ball not in play). What do the inputs have to be before the circuit transitions to S0 (which corresponds to "game commences")?
Question 4:
Suppose the circuit is in state S11 (i.e., ball is at LED 1 and is proceeding past players). For what inputs will the circuit hold its state? For what inputs will the circuit transition to S12 (ball out of play)? For what inputs will the circuit transition to S1 (ball proceeds down the court)?
Task 4:
Draw the ASM chart for the Court Display circuit.
To design the Court Display, you will use the following parts: 74163 (synchronous 4-bit up counter), 2716, and the 74138 (3:8 decoder/demultiplexer). The parts are connected as follows.
The following is a brief description of the 74163 4-bit up counter , a generic 3-to-8 decoder, and the 74138 3-to-8 decoder. Recall that the 74163 is a 4-bit synchronous up counter. The fact that it's synchronous means that its state changes only at clock transitions. If its Clear input is 1 then its count (QD,QC,QB,QA) is cleared. If ENP and ENT are both 1 then the count is incremented by one (i.e., it counts). If the Load is 1 then the value at (D,C,B,A) is loaded into the counter. The 74163 is used as the state register. (See pg. 337 of the textbook for a description of the '163.)
A generic 3-to-8 decoder (or 3-to-8 demultiplexer or demux, or sometimes written as 3:8 demultiplexer or decoder, etc) has a single "data" input G1 (which is sometimes called the "enable" input), three select inputs (C,B,A), and eight outputs (Y0, Y1,..., Y7).
The select input value is a 3-bit number that determines which output that G1 will be connected to. For example, suppose (C,B,A) = (0,1,1). Since 011 corresponds to the value 3, the output Y3 is connected to G1. As another example, suppose (C,B,A) = (1,0,1). Then Y5 = G1. If an output is not selected then its value is 0. The following is the truth table of a 3-to-8 decoder.
Inputs Outputs
Enable Select
G1 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 X X X 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 0 0 0 0
1 0 0 1 0 1 0 0 0 0 0 0
1 0 1 0 0 0 1 0 0 0 0 0
1 0 1 1 0 0 0 1 0 0 0 0
1 1 0 0 0 0 0 0 1 0 0 0
1 1 0 1 0 0 0 0 0 1 0 0
1 1 1 0 0 0 0 0 0 0 1 0
1 1 1 1 0 0 0 0 0 0 0 1
(See pp. 187-188 of the textbook for another description of a decoder/demultiplexer.)
The 74138 3-to-8 decoder will be used to drive the six LEDs (i.e., LED 1, LED 2,... LED 6). It has the inputs A, B, C, G1, G2A, and G2B, and the outputs Y0, Y1, ..., Y7. (For a description of the '138, see pp. 193-194 of the textbook.) The '138 has two additional inputs: G2A and G2B. Both must be L for the decoder to work. Assuming both G2A and G2B are L, the following is the voltage table of the 74138.
Inputs Outputs
Enable Select
G1 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
L X X X H H H H H H H H
H L L L L H H H H H H H
H L L H H L H H H H H H
H L H L H H L H H H H H
H L H H H H H L H H H H
H H L L H H H H L H H H
H H L H H H H H H L H H
H H H L H H H H H H L H
H H H H H H H H H H H L
It is a 3:8 decoder assuming positive logic at inputs and negative logic at outputs.
For the Court Display circuit, let d2, d1, d0 (from the 2716) be connected to C, B, A of the '138. The outputs Y1, Y2, ..., Y6 of the '138 correspond to L1, L2,..., L6, respectively. Hence, the outputs L1, L2,...., L6 have the negative logic convention. You should also have G1 = H, and G2A = L and G2B = L.
Question 5:
If the circuit is in state S0, what should the value of (d2,d1,d0) be?
Question 6:
If the circuit is in state S10, what should the value of (d2,d1,d0) be?
Question 7:
If the circuit is in state S12, what should the value of (d2,d1,d0) be?
Task 5:
Design the circuit in Xilinx. Use the following encoding for the states:
S0, S1, S2.... is represented by 0000, 0001, 0010,..., respectively.
Get a print out of your working circuit.
Attach the truth table that you used to program the 2732.
(Hint: Suppose the circuit is in state S11, and Run = 1. If SwC = 0 then the player has missed the ball and the next state should be S12. On the other hand, if SwC = 1 then the player hits the ball and the next state should be S1, i.e., the ball is at LED 2 and proceeds down court. To get to S12, have the '163 continue counting. To get to S1, have the '163 load the encoding for S1, which is 0001. Hence, the value at (D,C,B,A) for the '163 should be LLLH.)
Task 6:
With your group, build the Court Display on the protoboard.
Task 7:
Now that you've built these modules, it'd be nice to see if they work. On your protoboard, connect the modules together as shown below to get a single player game (similar to paddleball). This helps to determine if your modules are interoperable. Demonstrate to the TA that your circuit works.
