The Pipelined MIPs Project

Design a pipelined MIPS processor using Verilog HDL. The code must be synthesizable. All the information you need about the MIPS processor can be found in the textbook "Computer Organization and Design" by Patterson and Hennessy (publishers: Morgan-Kaufmann). The architecture for the pipelined MIPS can be found in Chapter 6 "Enhancing Performance with Pipelining". Your processor does not have to have interrupts, so you can skip Section 6.7. The set of instructions your processor should be able to execute are

add, sub, and, or, and slt.
addi, subi, andi, ori, and slti.
bne and beq.
j, jr, and jal.

As an option, you can put in an L2 cache unit. Read Sections 7.1, 7.2 and 7.3 about caches. Use direct mapped and write-through.

Find a Verilog HDL textbook to learn Verilog on your own. Here is an example:

M. Ciletti, "Modeling, Synthesis, and Rapid Prototyping with Verilog HDL," Prentice-Hall. This comes with the student version of the Xilinx Foundation Express.