EE 361L      Fall 2013
Under construction

Last updated July 5, 2013

Objectives

The laboratory course objectives are

The following are more details about the objectives.

The lab is Writing Intensive. Therefore, lab reports will be graded for writing style, which will count towards around 50% of the overall grade. Good communication skills are important for any successful engineer.

Topics Covered

The laboratories are organized as follows. Each lab assignment covers one or more lab sessions (3 hrs/session). 

Course Outcomes

Teaching Assistant (TA) Information

Instructions

  1. You must attend every lab on the scheduled days and times, and come on time. You may be excused only if you have a doctor's note with a valid reason. If you must miss a lab then contact the T.A. (email or telephone) before the Lab.
  2. Each individual is required to submit their own individual lab report except for Assignment 3 Computer Reports, which requires a group report. Lab reports will be collected at the beginning of the session, unless notified otherwise. No late reports will be accepted. Note that this laboratory satisfies the writing intensive (WI) requirement. Therefore, the reports will be graded on writing style. Each report must follow the format explained here
  3. Read lab handouts before coming to labs to help insure that assignments are completed on time.
  4. Use the computers and other equipment in the Laboratory for the intended experiments and not for personal use.
  5. Do not damage any kind of laboratory equipment. You can be held responsible.
  6. Follow the Lab Safety Rules for your own safety!!!

Grading Policy

Grading is based on lab assignments, which require demonstrations to the TA and written lab reports. For one of the assignments, the demonstration is an oral presentation.

Written lab reports and demonstrations are graded as follows:

Grades are based on the following standard curve:

Textbook and Reading Assignments

We have a textbook for the lab course, Advanced Digital Design with Verilog HDL by M. Ceiletti  Prentice-Hall.  It covers design methods for the Verilog Hardware Description Language (HDL) and field programmable gated arrays (FPGAs).  This will be useful for Lab Assignments 4.1, 4.2, and 5

List of Assignments


#
Lab Asssignment
#Weeks
[Points]

Report
Grading

Style
Report Due
Dates

0
Introduction

  • Meet Teaching Assistant (TA)
  • Take and Pass Electrical Safety Quiz. Read the electrical safety rules before lab. The TA will go over the rules and then you will take the quiz. After passing the quiz, you can sign the safety form and are then allowed to do the lab assignments.
  • Form lab groups. Lab groups have two members except one group of three if there is an odd number of students.
  • Get or reactivate your wiliki account -- see the instructor if you're unfamiliar with wiliki.

1 Week
[0 pts]



1
Measurement of TTL characteristics

1 Week
[10 pts]
Grading
with
revision
First due date:  TBA
Revision due date:  TBA
2.1
Micro-Controllers: Introduction to the PIC 16F84A

  • Tutorial on the PIC 16F648A. This the first of a three part overview of the PIC 16F648A. This will take about 60-90 minutes to read.
  • MPLab Tutorial. This is a tutorial for the software you will use, the MPLab. It is an integrated development environment which includes a C compiler, simulator, and programmer. This will take about 30 minutes to read.

More Information
1 Week
[10 pts]
Loose grading
Due date:  TBA
2.2
Read before lab (30 minutes of reading): Part 2 of overview of PIC
Read before lab (15 minutes of reading): Micro-Controllers: Traffic Light Controller
Download testlab2.c
1 Week
[10 pts]
Regular
grading
Due date:  TBA
2.3
Read before lab (30 minutes of reading)Part 3 of overview of PIC
Read before lab (30 minutes of reading)Micro-Controllers: Interrupts and Simulation in MPLAB
1 Week
[10 pts]
Grading
with
revision
First due date:  TBA
Revision due date:  TBA
3
CPU Research
  • TA will give an overview of CPUs during a lab session
  • Oral Presentation
    • Presentation schedule: November 1. Details to be announced. Since we have large sections, we will have to start the morning section earlier and have the afternoon section end later. Each student will have about 8 minutes to present.
4 Weeks
[30 pts]
Grading
with
revision
First due date: Nov. 1
Revision due date:  TBA after you receive comments from your first submission
4.1
Verilog HDL and FGPAs: Part I -- under construction
(It will cover introduction to FPGAs, FPGA design tools such as Xilinx Webpack, Digilent Basys boards, proper Verilog HDL design and functional simulation and testing.)

Reading Assignment:  Ciletti, For the first lab session read Chap 1 and 8.  Optional reading is Chap 2.  For the second lab session read Chapter 4.
1 Week
[10 pts]
Loose
grading
Due date:  TBA
4.2
Verilog HDL and FGPAs: Part II -- under construction
(It will cover synthesis and post synthesis design tasks.)

Reading Assignment:  Ciletti.  For the first lab session read parts of Chap 6, and for the second lab session read parts of Chap 11.
1 Week
[10 pts]
Loose
grading
Due date:  TBA
5
Final Project: Pipeline CPU Design and Implementation -- Under Construction
4 Weeks
[40 pts]
Regular
grading
Due date:  TBA