EE 361L      Fall 2009

Last updated August 18, 2009

Objectives

The laboratory course objectives are (i) to apply micro-controllers to design, (ii) research issues of processor design, (iii) understand and apply HDL and FPGA technologies and tools, (iv) understand and implement a processor, (v) write technical reports, and (vi) give a clear oral presentation on a technical topic.  The following are more details about the objectives.

The lab is Writing Intensive. Therefore, lab reports will be graded for writing style, which will count towards around 50% of the overall grade. Good communication skills are important for any successful engineer.

Topics Covered

The laboratories are organized as follows, where each lab assignment covers one or more lab sessions (3 hrs/session). 

Course Outcomes

Teaching Assistant (TA) Information

Instructions

  1. You must attend every lab on the scheduled days and times, and come on time. You may be excused only if you have a doctor's note with a valid reason. If you must miss a lab then contact the T.A. Ashok (email or telephone) before the Lab.
  2. Each individual is required to submit their own individual lab report except for Assignment 3 Computer Reports, which requires a group report. Lab reports will be collected at the beginning of the session, unless notified otherwise. No late reports will be accepted. Note that this laboratory satisfies the writing intensive (WI) requirement. Therefore, the reports will be graded on writing style. Each report must follow the format explained here
  3. Read lab handouts before coming to labs to help insure that assignments are completed on time.
  4. Use the computers and other equipment in the Laboratory for the intended experiments and not for personal use.
  5. Do not damage any kind of laboratory equipment. You can be held responsible.
  6. Follow the Lab Safety Rules for your own security!!!

Grading Policy

Grading is based on lab reports and demonstrations, i.e., presentations to the TA that the assignment was carried out partially or to completion. Each assignment is graded as follows: Grades are based on the following standard curve:

Textbook and Reading Assignments

We have a textbook for the lab course, Advanced Digital Design with Verilog HDL by M. Ceiletti  Prentice-Hall.  It covers design methods for the Verilog Hardware Description Language (HDL) and field programmable gated arrays (FPGAs).  This will be useful for Lab Assignments 4.1, 4.2, and 5

Software Tools

List of Assignments


#
Lab Asssignment
#Weeks
[Points]

Report
Grading

Style
Report Due
Dates

0
Introduction

Read instructions to write lab reports. All lab reports must conform to the format.
Get or reactivate your wiliki account as soon as possible.
1 Week
[0 pt]
No report due

1
Measurement of TTL characteristics

Read
1 Week
[10 pts]
Grading
with
revision
First due date:  TBA
Revision due date:  TBA
2.1
Micro-Controllers: Introduction to the PIC 16F84A

More Information
1 Week
[10 pts]
Loose grading
Due date:  TBA
2.2
Micro-Controllers: Traffic Light Controller 1 Week
[10 pts]
Regular
grading
Due date:  TBA
2.3
Micro-Controllers: Interrupts and Simulation in MPLAB 1 Week
[10 pts]
Grading
with
revision
First due date:  TBA
Revision due date:  TBA
3
CPU Presentations
  • TA will give an overview of CPUs during a lab session
  • Oral Presentation
    • Presentation schedule:  TBA.  Each student has about 8 minutes to present.
4 Weeks
[30 pts]
Grading
with
revision
First due date: TBA
Revision due date:  TBA
4.1
Verilog HDL and FGPAs: Part I
(It will cover introduction to FPGAs, FPGA design tools such as Xilinx Webpack 5.2, XSA 100 development board, proper Verilog HDL design and functional simulation and testing.)

Reading Assignment:  Ciletti, For the first lab session read Chap 1 and 8.  Optional reading is Chap 2.  For the second lab session read Chapter 4.
1 Week
[10 pts]
Loose
grading
Due date:  TBA
4.2
Verilog HDL and FGPAs: Part II
(It will cover synthesis and post synthesis design tasks.)
The sessions will be held during the same period as Lab Assignment 5 Final Project.

Reading Assignment:  Ciletti.  For the first lab session read parts of Chap 6, and for the second lab session read parts of Chap 11.
1 Week
[5 pts]
Loose
grading
Due date:  TBA
5
Final Project: Pipeline CPU Design and Implementation -- Under Construction
4 Weeks
[40 pts]
Regular
grading
Due date:  TBA