EE 361 Fall 2008 Lecture Schedule and Notes

What's New

Overview

This is an overview of the topics to be covered.

I. Instruction Set Architecture (and Assembly Language): Approximately 4 weeks

Instructions that a computer can execute.
Assembly language
Compiling, and other related operating system software.
Data representation
Subroutines and Stacks
Exceptions (interrupts)

II. MIPs Processor Design: Approximately 3.5 weeks

Review of digital circuit parts and design techniques.
- Parts: registers, register files, RAM, combinational circuits, sequential circuits (Mealy machines), multiplexers, demultiplexers, and tri-states.
- Design Techniques: modular design, ASM charts, state diagrams, design procedure from state diagrams or ASM charts to sequential circuits.
- Verilog HDL -- structural Verilog.
Single-Cycle MIPS Processor
Multi-Cycle MIPS Processor
Performance: critical paths, propagation delays, set-up times, holding times.

III. Processor Component Design: 3.5 weeks

ALU: implementing integer arithmetic, iterative partitioning in space and time, multiplication, division, and Booth's algorithm.
Controller: design techniques such as one-hot encoding and microprogramming.
Performance.

IV. Other Important Stuff: 2 weeks

Memory Hierarchy: caching, virtual memory.
Floating point

Lecture Notes

Can be found at myuhportal EE 361 class web site

Instruction Set Architecture - Assembly Language (MIPS)

Topic	Subtopic	Reading Assignments		Dates
Topic	Subtopic	Textbook	Notes	Dates
Introduction	Introduction and machine performance.	Sec. 1.1 - 1.3	Overview and Intro	2 days
Instruction Set Architecture -- Assembly Language (MIPS)	Instructions and operands.	Sec. 2.1 - 2.3	MIPSa 1-15	2 days
	Instruction format, assembly language, logic operations, and branching/jumping.	Sec. 2.4 - 2.6,	MIPSa 16-43	2 days
	C functions and stacks.	Sec. 2.7.	MIPSb 1-18	2 days
	Addressing modes, immediate addressing, PC-relative adressing.	Sec. 2.8 (this section is about text characters, which will be discussed later in the course), 2,9	MIPSb 19-29	1 day
	Passing parameters through registers and stack	Sec. 2.10, and A.1. Note that the topics of Sec 2.10 will be discussed in a later lecture (MIPSc 20-30 "Big picture".)	MIPSc 1-11	1 day
	Function calls in MIPs, stack frames, some details about the MIPs assembly language.	Sec. A.2, A.5, and A.6.	MIPSc 12-19	1 day
	Big picture: assemblers, linkers, and loaders.	Sec. A.3, A.4,, 2.10 - 2.12	MIPSc 20-30	1 day
	Mopping up: arrays versus pointers, properties and rules of thumb, CISC.	Secs. 2.13. Optional reading: 2.15	MIPSc 31-33	1 day
Review of number representation and a brief discussion of exceptions	Review positional number systems, addition, conversion from binary to octal and hex, unsigned integers, signed numbers.	Sec. 3.1-3.2.	Arith 1-14	1 day
	Signed numbers, twos complement, negation, addition	Sec. 3.3.	Arith 15-28	1 day
	Interrupts and Exceptions	Read Section A.7 of Appendix A (in the CD ROM of the textbook). It refers to SPIM or PCSPIM which are simulators of the MIPS Processor It also references the MIPS registers ($0-$31) differently (see Figure A.6.1 on page A-24 of the appendix).	IO 1-18	2 days
Review of digital logic, and a review of hardware description languages and FPGAs	Review of Basic Parts: combinational circuits, truth tables, logic operations, and Verilog HDL and modules	CircRev 1-11. No textbook reading assignment	CircRev 1-11	1 day
	Sequential circuits and verilog.	CircRev 12-23. Verilog manual reading assignment from homework. No textbook reading assignment.	CircRev 12-23	1 day
	Sequential Circuits, Mealy machines, ASM charts, and state diagrams.	CircRev 22-32. No textbook reading assignment.	CircRev 22-32	1 day
	Overview of FPGAs	No textbook reading assignment.	EDA, Hardware Design Tips	2 days
Single cycle MIPS processor	Overview of datapath	Sec. 5.1-5.3.	SingleMIPS 1-13	1 day
	Continue overview of datapath	Sec. 5.4.	SingleMIPS 14-26	1 day
	Control		SingleMIPS 27-38	2 days
Multi cycle MIPS processor	Introduction	Sec. 5.5.	MultiMIPS 1-8	1 day
	Datapath	Sec. 5.5.	MultiMIPS 9-15	1 day
	State diagram of controller		MultiMIPS 16-24	1 day
	Hardware design tips on verilog and 16 bit version if Single Cycle MIPS		Hardware design tips	2 days
	One hot encoding		MultiMIPS 25-34,47-48	1 day
	Microprogramming	Sec. 5.7. and App. C. Optional Reading: Sec. 5.9.	MultiMIPS 35-48.	1 day
	Assessing and understanding performance	Sec. 4.1-4.3	To be determined	2 days
Processor Component Design: ALU	Logic operations (AND, OR, Compl., XOR), simple ALU by iterative partitioning in space.	Sec. 3.3	ALU 1-4,70-74	1 day
	Carry-lookahead and carry-save, shifting, barrel shifter, cross-bar switch.		ALU 5-19	1 day
	Three versions of unsigned multiplying. Booth's algorithm for signed multiply.	Sec. 3.4	ALU 20-43	1 day
	Division.	Sec. 3.5	ALU 44-54
	Floating point definitions and hardware	Sec. 3.6	ALU 55-69.
Memory Hierarchy	RAM -- dynamic and static	Sec. 7.1-7.2	Memory 1-14
	Caches		Memory 15-43
	Virtual Memory	Sec. 7.3.	Memory 44-99