EE 361L

Lab 5 Final Project

Deadlines

• December 9, 2008 TUESDAY during lab:  Last day to submit and demonstrate a working multicycle MIPS under Stages 1 through 5. You can demonstrate stages earlier.
  
• December 15, 2008 MONDAY, 12 NOON:  Last day to submit the laboratory report.  Each student submits their own report.  The report must be in pdf format, and must be submitted as an attachment by email (no late submissions will be accepted, since we need several days to grade the reports)
  
• To:  alanxiachen@hotmail.com (Teaching Assistant)
  
• Cc: galens@hawaii.edu
• Subject:  EE 361L Lab 5 Report
• Attach your report (pdf) and zipped file with the Verilog code of the last step you got working.  For example, if you got Step 4 but not Step 5 then submit the working code for Step 5 (see below for the "Steps").  Your code should be in a zipped folder that includes all the verilog code, veriwell project file, and README file.  The folder should be complete so that running the project file using veriwell will simulate the code correctly.  The README file should be a word doc or text file that explains the Step that you completed (e.g., "Step 4 was completed"), your name, date, and instructions of how to run your code using veriwell.  Note that the instructions can be quite brief.  Whoever is grading your assignment will open the file and run the project according to your instructions in the README file.  If it fails then that will reflect in your grade.
  

Instructions

You will build the multicycle MIPSL processor in verilog, which is a 16-bit version of the multi cycle MIPS.  It has the same instruction set as the single cycle MIPS-L of Homework 9.  Unlike the single cycle MIPSL, this computer takes multiple cycles per instruction.  The state diagram of the controller of the MIPSL is basically Figure 5.28 in the textbook but where the data and address are 16 bits, and the register file is made up of 8 registers.  The components such as the ALU is the same as in Homework 9.  Note that all arithmetic and logic operations are done in the ALU with the exception of sign extension and shifting. 

The controller of the MIPSL is a state machine with

• State 0:  Instruction fetch
• State 1: Instruction decode/register fetch
• State 2:  Memory address computation (for sw/lw)
• State 3: Memory access for lw
• State 4: Memory read completion for lw
• State 5: Memory access for sw
• State 6: R-type execution
• State 7: R-type completion
• State 8: BEQ
• State 9: Jump

• Download EE361L-Step-1(zipped):  This are the MIPS-Parts.V as in Homework 9 except the DMemory module is replaced with Memory module that also includes the instruction memory (recall that multicycle MIPS has only one memory that holds data and instructions).  IM1.V has the (instruction memory) IM module that is a ROM that has a program that multiplies 3 with 5.  The MIPSL must implement the instructions in IM1.V  such as add, addi, beq, and j.
  
• Download EE361L-Step-1b(zipped):  This has the incomplete verilog module for the multicycle MIPS:  MMIPS.V, and the testbench.  Note that the MIPS is a sequential circuit, so the controller requires a state register.  As a hint, it is suggested that the controller have two parts.  One part will update the state and can be implemented with a procedural always that is triggered on clock transitions.  The second part will use the state and other inputs to control the data path.  This is a combinational circuit, and can be implemented with a procedural always.
• Trace file (zipped word doc):
  

• Folder with IM2Lab.V (program for this project), testbench and trace file for Step 2 (simulate program 2), testbench for Step 3 (FPGA implementation)
• Step 2 is to simulate the MIPSL using the program in IM2Lab.V.  This program is similar to the second program in Hw 9.  There is a testbench and trace file.  Demonstrate your simulation to the TA.
• Step 3 is to implement the computer in an FPGA.  Note there is a verilog file FPGA-Prog2.V which has a module for the computer, composed of the MIPSL and memory/IO.  The computer has outputs to the 7 segment display and switches.  The TA will give you instructions on implementing the circuit on the FPGA boards which includes connecting the IO to the displays and switches on the boards.  Demonstrate your working FPGA to the TA.
  

• Folder with IM3Lab.V (program for this project), testbench and grace file for Step 4.
• Step 4 is to simulate the MIPSL using the program in IM3Lab.V in veriwell.  Your processor must run jr and jal instructions.  (Hints:  jr is an R type instruction.  So the fact that the instruction will modify the pc is in the function field, not the opcode field.  One approach to implement this is to have the ALU controller indicate a jr instruction with a new output port.  This can be used by the PC logic to determine if the PC should load a value from the register file.  In my implementation, I also have an additional output to indicate when the PC should load in case of a jr instruction.  This will occur in the last R type state.  Note that the PC should not load if the R type instruction is not jr.)
  

Grading

• Writing Style:  20 points is for writing style of the written report
• MIPS-L Implementation:  20 points depends on the capabilities of the multicycle MIPS-L you implement in verilog.  You must demonstrate to your TA that your MIPS-L can execute the following programs correctly using veriwell or any other simulator that the TA has taught you

• Step 1:  Simulate MIPSL with Program 1
  
• Step 2:  Simulate MIPSL with Program 2
  
• Step 3:  Implement MIPSL with Program 2 in an FPGA
  
• Step 4:  Simulate MIPSL with Program 3