Last updated June
2008
The lab is Writing
Intensive. Therefore, lab reports will
be graded for writing style, which will count towards around 50% of the
overall grade. Good communication skills are important for any
successful engineer.
| # |
Lab
Asssignment |
#Weeks
[Points] |
Report Grading Style |
Report
Due Dates |
| 0 |
Introduction Read instructions to write lab reports. All lab reports must conform to the format. Get or reactivate your wiliki account as soon as possible. |
1 Week [0 pt] |
No report due |
|
| 1 |
Measurement
of TTL characteristics Read
|
1 Week [10 pts] |
Grading with revision |
First due date: TBA Revision due date: TBA |
| 2.1 |
Micro-Controllers:
Introduction to
the PIC 16F84A More Information |
1 Week [10 pts] |
Loose grading |
Due date: TBA |
| 2.2 |
Micro-Controllers: Traffic Light Controller | 1 Week [10 pts] |
Regular grading |
Due date: TBA |
| 2.3 |
Micro-Controllers: Interrupts and Simulation in MPLAB | 1 Week [10 pts] |
Grading with revision |
First due date: TBA Revision due date: TBA |
| 3 |
CPU
Presentations
|
4 Weeks [30 pts] |
Grading with revision |
First due date: TBA Revision due date: TBA |
| 4.1 |
Verilog
HDL and FGPAs: Part I (It will cover introduction to FPGAs, FPGA design tools such as Xilinx Webpack 5.2, XSA 100 development board, proper Verilog HDL design and functional simulation and testing.) Reading Assignment: Ciletti, For the first lab session read Chap 1 and 8. Optional reading is Chap 2. For the second lab session read Chapter 4. |
1 Week [10 pts] |
Loose grading |
Due date: TBA |
| 4.2 |
Verilog
HDL and FGPAs: Part
II (It will cover synthesis and post synthesis design tasks.) The sessions will be held during the same period as Lab Assignment 5 Final Project. Reading Assignment: Ciletti. For the first lab session read parts of Chap 6, and for the second lab session read parts of Chap 11. |
1 Week [5 pts] |
Loose grading |
Due date: TBA |
| 5 |
Final Project: Multi-Cycle CPU Design and Implementation | 4 Weeks [40 pts] |
Regular grading |
Due date: TBA |