EE 361L University of Hawaii

Lab 4.2. Verilog HDL and FPGAs:  Part II

• Objective: Another assignment to become familiar with Verilog HDL and FPGAs. 
  
• Assignment: 
• Here is the Assignment
• Here are the files referred to in the assignment
• Parts4-2.V
• TestParts4-2.V
• testbenchParts4-2.V
• Core4-2.V
• testbenchCore4-2.V
• TrafficLight.V
• testbenchTrafficLight.V
  
• Lab Report: In your lab report, explain what you and your lab team did, and describe any problems that you encountered.  The lab TA will explain more about what to write in your report and how long it should be.  Grading style is loose grading.