EE 361L University of Hawaii

Fall 2004

Lab 4.1. Verilog HDL and FPGAs:  Part I

• Objective: Become familiar with Electronic Design Automation (EDA).  Not much design here.  Just become familiar with the tools.
• Assignment: 
• Lab 4.1 assignment (pdf)  
• Other Files:
• Design flow (pdf):  Explains hardware design process
• Webpack (pdf):  An introduction to Xilinx WebPack 5.2i
• ModelSim (pdf):  Tutorial on ModelSim from Stanford
• FPGA boards (pdf):  Explains testing XSA-100 and general precautions
• Examples in verilog for the tutorials
• setLED.ucf
• setLED.v
• Common_Pin_Assignments.pdf
  
• Lab Report: In your lab report, explain what you and your lab team did, and describe any problems that you encountered.  The lab TA will explain more about what to write in your report and how long it should be.  Grading style is loose grading.