EE 361 Homework 8B

Due: December 5, 2005 (Monday) by 1230pm

Get started on it as soon as possible and be diligent. It will help you finish the EE 361L final project.

Make a project using veriwell and add these files. Then run.

Problem 1 [8 pts]

You will build the single cycle MIPS-L processor in verilog, whichis a 16-bit version of the single cycle MIPS. A description of the MIPS-L processor can be found in the Hardware Design Tips notes as follows. Go to the EE 361 web site --> Lecture schedule and notes --> Lecture notes --> Hardware Design Tips.

Your MIPS-L module should look like this.

module MipsL(daddr,iaddr,dwrite,aluout,memwrite,clock,reset,dread,iread);
output [15:0] iaddr;          // Address bus to instruction memory
output [15:0] daddr;            // Address bus to data memory
output [15:0] aluout;           // Output of the ALU used for debugging.
output memwrite;                // Output to write enable of data memory

input clock;
input reset;    // Reset to clear PC. If reset = 1 then next clock transition
//     will clear PC.
input [15:0] dread;          // Read data bus from data memory
output [15:0] dwrite;        // Write data bus to data memory
input [15:0] iread;    // Data bus from instruction memory

.
.
.
endmodule

Instructions

Do ONE of the three stages below.

Each stage requires creating a verilog version of a processor (either MIPS-L1, MIPS-L2, or MIPS-L3) and including it into a PC folder. Zip the folder and email it as an attachment to the grader as follows:

TO: agomera@hawaii.edu
SUBJECT: Hw8B
CC: sasaki@spectra.eng.hawaii.edu

The verilog processor MUST WORK. You receive no credit if the processor has errors or only partially works. Therefore, turn in a processor that absolutely works.

Hint: The output of simulations of the instructor's implementations (word doc) of MIPS-L1, MIPS-L2, and MIPS-L3.

STAGE 1: Implement the R type (excluding jr) instructions and the following instructions: addi, j, and beq. Call this the MIPS-L1 processor. If completed, it is 6 points out of 8.

Your processor should run the following program:

     add   $1,$0,$0      # $1 = 0
     addi $2,$0,$5      # $2 = 5
L1: beq $1,$2,Skip
     addi $1,$1,1       # Increment $1
     j     L1
Skip:
     addi $1,$0,2       # $1 = 2
     j     L1

Create a verilog MIPS-L1 processor. Create a project labeled MIPSL1-YourLastNameFirstInitial (e.g., "MIPSL1-SasakiG") that includes your processor and

Put your project, your verilog MIPS-L1 processor, the testbench, and instruction memory into a PC folder labeled HW8B-L1-YourLastNameFirstInitial. The grader should be able to load your project using veriwell, and then run the simulation properly.

STAGE 2: Have the processor implement the following additional instructions: lw and sw. Call this the MIPS-L2 processor. This completes the homework. If completed, it is worth 8 points out of 8.

Your processor should run the following program:

# This program reads and writes to data memory
L1:   addi   $1,$0,5    # $1 = 5
      addi   $2,$0,7    # $2 = 7
      addi   $3,$0,6    # $3 = 6
# Swap values between registers $1 and $2
L2:   sw     $1,2($3)
      sw     $2,4($3)
      lw     $2,2($3)
      lw     $1,4($3)
      beq    $3,$0,L1
      addi   $3,$3,-2
      j      L2

Create a verilog MIPS-L2 processor. Create a project labeled MIPSL2-YourLastNameFirstInitial that includes your processor and

Put your project, your verilog MIPS-L2 processor, the testbench, and instruction memory into a PC folder labeled HW8B-L2-YourLastNameFirstInitial. The grader should be able to load your project using veriwell, and then run the simulation properly.

STAGE 3 (Bonus points):   Have the processor implement all the instructions (including jr and jal). Call this the MIPS-L3 processor. This is bonus and your score will be 8 points plus 8 bonus points.

Your processor must be connected to data memory (RAM). Note that jal will store the return address in register $7. Your processor should run the following program:

# This program reads and writes to data memory
L1:   addi   $1,$0,5    # $1 = 5
      addi   $2,$0,7    # $2 = 7
      addi   $3,$0,6    # $3 = 6
# Swap values between registers $1 and $2
L2:   jal    L3
      beq    $3,$0,L1
      addi   $3,$3,-2
      j      L2
L3:   sw     $1,2($3)
      sw     $2,4($3)
      lw     $2,2($3)
      lw     $1,4($3)
      jr     $7

Create a verilog MIPS-L3 processor. Create a project labeled MIPSL3-YourLastNameFirstInitial that includes your processor and

Put your project, your verilog MIPS-L3 processor, the testbench, and instruction memory into a PC folder labeled HW8B-L3-YourLastNameFirstInitial. The grader should be able to load your project using veriwell, and then run the simulation properly.