Problem A (Memory mapped IO): (2 pts) One of the common ways to implement IO is to make Input/Output (IO) hardware look like memory cells. Then memory accesses (e.g., lw and sw) are used by software to interact with the hardware.
The following is an example of IO hardware. The example hardware is the receiver circuitry from a computer keyboard. The hardware consists of two memory cells:
Recall ASCII is the way text characters are represented in binary. For example, the 8-bit number with value 65 represents the character "A". In the C language, char data type is in the ASCII form.)
The following assembly language program implements getchar(),
C function that gets a character from the keyboard. It assumes that the
character is returned in $2 (in the least significant byte).
lui $t0,0xffff # Load the upper half of $t0 with
# 1111111111111111, and the lower
# half with 0000000000000000.
lbu $at,0xc($t0) # Load $at with Receiver Control Reg.
# Here we use the "load byte
# unsigned" instruction (see pg.
andi $at,$at,2 # Mask all bits in $at except bit 1.
# Note that the mask is the
# constant 2, which is
# 0000..00010 in binary.
beq $0,$at,wait # If no new ACII byte then wait.
lbu $2,0x8($t0) # Put new ASCII byte from Receiver
# Data Register into $2
Now there are two IO registers to transmit ASCII charcters to a computer terminal.
Write an assembly language subroutine that implements putchar(char
c), the C function that outputs a character. The argument "c",
which is an ASCII byte, is passed through the least signifcant byte of
register $a0. You may use registers $at and $t0 for temporary storage.
Your assembly language subroutine have a comment line at the top
that has your name and the date, e.g.,
# Author: John Doe. Date: 10/14/05
By the way, these little programs are called drivers.
Problem B (not graded, 0 pts) In the Bucknell Verilog Handbook, there's a First Verilog Program. Get that program to work. Use the verilog simulator called Veriwell. There's a copy of Veriwell in the "Veriwell" Folder on the EE PC Server (it has a green square icon). You can also download a zipped version of Veriwell from our EE 361 web site. Skim through the Bucknell Verilog Handbook and in particular Sections 1 and 2. Run the Veriwell simulator. The handbook has description of using the Veriwell simulator in Section 3, which you should skim through as well. But it's for an old version of the simulator. The following are some hints for the simulators we have on the PCs:
It's important to do the problem even though
it's not graded.
Problem C (2 pt). You will design a verilog module called "Lights". Use the editor in veriwell to create the file for the module, and label it "YourLastName-FirstInitial-HWC.v". The first line of the file should have "EE 361 Homework 5 Problem C," your name, and date.
The circuit has the following ports: 4-bit output port "q", a clock input "clock", and a 2-bit select input "s". The select determines one of four possible modes for the circuit:
Your verilog module should have the following form:
//EE 361 Homework 7 Problem A, John Doe, October 19, 2004[Hint: The lights circuit should have a 2-bit state. It should be comprised of a procedural-always (and case statement) that updates the state, and another-procedural always that is used to convert the state value to the appropriate output value. The first procedural-always corresponds to a sequential circuit, and the second corresponds to a combinatorial circuit.]
module Lights(q, clock, s);
output [3:0] q;
input [1:0] s;
. fill in here (see below for a hint).
After designing the Lights module, create a testbench file using the veriwell's editor. The following is a suggestion (warning: could be buggy).
reg [1:0] tests, // This is connected to the input of the Lights circuit.
reg clock; // This will be used to generate a clock signal.
wire [3:0] testq; // This is connected to the output of the Lights circuit.
// We instantiate the Lights circuit into our testbench, and connect the testbench variables to
// its ports.
// The following is our clock generator which creates a clock signal with period of 2 time units.
initial clock = 0; // initializes clock to 0
always #1 clock = ~clock; // inverts clock every 1 time unit.
// We will control the value of the select input of the Lights circuit so that it first
// resets, then rotates to the left for 10 time units (or 5 clock cycles), hold its value for 4 time units,
// and then rotate to the right for 10 time units (or 5 clock cycles).
tests = 2;
tests = 1;
tests = 3;
tests = 0;
// Next use "display" and "monitor" to output (probe) the
// values of the circuit, to see if it works. This is left for you to do.
// The Bucknell Verilog handbook has some examples.
Now create a project and test your circuit. After debugging turn in the file that
has the Lights module as per the instructions above. Do not turn in your test bench.
[End of homework]