EE 361L

Lab 5 Final Project

Hi folks, added to this web page is an alternate description of the project. This is higlighted in RED.

Last Update: Nov. 29, 2005

Due: December 6, 2005 (tuesday) during the lab period

You will build the multicycle MIPS-L processor in verilog, which is a 16-bit version of the multi cycle MIPS. It has the same instruction set as the single cycle MIPS-L of Homework 8. The instruction set can be found in the Hardware Design Tips notes as follows. Go to the EE 361 web site --> Lecture schedule and notes --> Lecture notes --> Hardware Design Tips.

Your MIPS-L module should look like this.

module MipsL(daddr,iaddr,dwrite,aluout,memwrite,clock,reset,dread,iread);
output [15:0] iaddr;          // Address bus to instruction memory
output [15:0] daddr;            // Address bus to data memory
output [15:0] aluout;           // Output of the ALU used for debugging.
output memwrite;                // Output to write enable of data memory

input clock;
input reset;    // Reset to clear PC. If reset = 1 then next clock transition
//     will clear PC.
input [15:0] dread;          // Read data bus from data memory
output [15:0] dwrite;        // Write data bus to data memory
input [15:0] iread;    // Data bus from instruction memory

.
.
.
endmodule

ALTERNATELY, the multicycle MIPS-L should look like this

// Alternate RED VERSION
module MipsL(addr,writedata,aluout,memwrite,clock,reset,memdata);
output [15:0] addr;           // Address bus to memory
output [15:0] aluout;           // Output of the ALU used for debugging.
output memwrite;                // Output to write enable of data memory

input clock;
input reset;    // Reset to clear PC. If reset = 1 then next clock transition
//     will clear PC.
input [15:0] memdata;      // Read data from memory
output [15:0] writedata;     // Write data to data memory
.
.
.
endmodule

Your multicycle MIPS-L should execute the following three programs correctly.

PROGRAM 1: Your MIPS-L must be able to execute the R type instructions (excluding jr) and the following instructions: addi, j, and beq.

     add   $1,$0,$0      # $1 = 0
     addi $2,$0,$5      # $2 = 5
L1: beq $1,$2,Skip
     addi $1,$1,1       # Increment $1
     j     L1
Skip:
     addi $1,$0,2       # $1 = 2
     j     L1

The following are testbench, instruction memory (with Program 1), and data memory (RAM). They may be buggy.

Alternate RED VERSION (note it's the almost same as the above because we're not writing to memory)

PROGRAM 2: Your MIPS-L must be able to execute R type (excluding jr), addi, j, beq, lw and sw.

# This program reads and writes to data memory
L1:   addi   $1,$0,5    # $1 = 5
      addi   $2,$0,7    # $2 = 7
      addi   $3,$0,6    # $3 = 6
# Swap values between registers $1 and $2
L2:   sw     $1,2($3)
      sw     $2,4($3)
      lw     $2,2($3)
      lw     $1,4($3)
      beq    $3,$0,L1
      addi   $3,$3,-2
      j      L2

The following are testbench, instruction memory (with Program 2), and data memory (RAM). They may be buggy.

Alternate RED VERSION (note that RAM starts at address 64, and program starts at address 0)

# This program reads and writes to data memory
L1:   addi   $1,$0,5    # $1 = 5
      addi   $2,$0,7    # $2 = 7
      addi   $3,$0,64 # $3 = 64 <-- here's the change
# Swap values between registers $1 and $2
L2:   sw     $1,2($3)
      sw     $2,4($3)
      lw     $2,2($3)
      lw     $1,4($3)
      beq    $3,$0,L1
      addi   $3,$3,-2
      j      L2

PROGRAM 3 (Bonus points):   Your MIPS-L must be able to execute all the instructions (including jr and jal).

# This program reads and writes to data memory
L1:   addi   $1,$0,5    # $1 = 5
      addi   $2,$0,7    # $2 = 7
      addi   $3,$0,6    # $3 = 6
# Swap values between registers $1 and $2
L2:   jal    L3
      beq    $3,$0,L1
      addi   $3,$3,-2
      j      L2
L3:   sw     $1,2($3)
      sw     $2,4($3)
      lw     $2,2($3)
      lw     $1,4($3)
      jr     $7

The following are testbench, instruction memory (with Program 3), and data memory (RAM). They may be buggy.

Alternate RED VERSION (note that RAM starts at address 64, and program starts at address 0)

# This program reads and writes to data memory
L1:   addi   $1,$0,5    # $1 = 5
      addi   $2,$0,7    # $2 = 7
      addi   $3,$0,64 # $3 = 64 <-- here's the change
# Swap values between registers $1 and $2
L2:   jal    L3
      beq    $3,$0,L1
      addi   $3,$3,-2
      j      L2
L3:   sw     $1,2($3)
      sw     $2,4($3)
      lw     $2,2($3)
      lw     $1,4($3)
      jr     $7

Grading

The total points for this lab is 40.

Writing Style: 20 points is for writing style of the written report
MIPS-L Implementation: 20 points depends on the capabilities of the multicycle MIPS-L you implement in verilog. You must demonstrate to your TA that your MIPS-L can execute the following programs correctly using veriwell or any other simulator that the TA has taught you

Program 1 --> 16 points
Program 2 --> 18 points
Program 3 --> 20 points

To receive the points, your MIPS-L must be absolutely correct for the particular program. If your MIPS-L does not run any of the programs correctly then the TA may award you partial credit of up to 12 points.