EE 361L University
Lab 4.1. Verilog HDL and FPGAs: Part I
- Objective: Become familiar with Electronic Design
Automation (EDA). Not much design here. Just become
familiar with the tools.
- Other Files:
- Lab Report: In your lab report, explain what you and your
lab team did, and describe any problems that you encountered. The
lab TA will explain more about what to write in your report and how
should be. Grading style is loose grading.