EE 361L -- Fall 2003

Last Update: 11/3/03

Objectives

The laboratory course objectives are (i) to apply micro-controllers to design, (ii) research issues of processor design, (iii) understand and apply HDL and FPGA technologies and tools, (iv) understand and implement a processor, (v) write technical reports, and (vi) give a clear oral presentation on a technical topic. The following are more details about the objectives.

1. Measurement of TTL Characteristics. You will measure current and voltages on the inputs and outputs of digital circuits, and then determine physical limitations of putting circuits together.
2. Micro-Controllers. There are three assignments to introduce micro-controllers, which are one-chip computers used for controlling systems, e.g., automobile engines, appliances, etc. They are relatively small and cheap digital circuits that are capable of complex control.
- You will use micro-controllers in circuit designs. In this way, you will see how computers are used as circuits.
- You will learn Input/Output (I/O) concepts including interrupts.
- You will see how software interacts with hardware.
- You will use the PIC micro-controller 16F84A and its support tools, such as the simulator and compiler.
3. Computer Reports. You will research a computer to understand its organization and how it works. You will present your findings in written and oral reports.
- You will practice technical research and self-studying technical information.
- You will practice your communication skills in explaining technical material.
- By attending presentations of other groups, you will get an overview of many processors.
4. Verilog HDL and FPGAs. Hardware description languages (HDL) and field programmable gated arrays (FPGAs) are powerful tools for computer circuit designers. HDLs resemble high-level programming languages but are used to specify digital circuits. The most popular HDLs are Verilog and VHDL. We will use Verilog, which resembles the C programming language. FPGAs are digital circuits on a chip that can be programmed (configured) and re-programmed. Due to their flexibility, they are used to quickly design and implement systems.
- You will write Verilog code that is synthesizable, i.e., code that can be translated into hardware.
- You will implement your Verilog code into FPGA circuits.
- You will check timing and understanding how proper design can improve performance (speed).
5. Multi-Cycle Processor Implementation. The final project is to design and implement a processor using synthesizable Verilog code. The processor will be a variation of the MIPS processor discussed in EE 361.

The lab is Writing Intensive. Therefore, lab reports will be graded for writing style, which will count towards around 50% of the overall grade. Good communication skills are important for any successful engineer.

Topics Covered

The laboratories are organized as follows, where each lab assignment covers one or more lab sessions (3 hrs/session).

Introduction. There is an introductory lab session covering procedures. There is no assignment
Measurement of TTL characteristics. Measurement of voltages and current of different TTL logic gates, followed by calculating characteristics such as fan-out and fan-in.

Assignment 1: The measurement and calculation of characteristics are covered.

Micro-controllers. An introduction to micro-controllers, e.g., PIC16F84A, including design applications.

Assignment 2.1. An introduction to the micro-controllers including tutorials on compiler, programming procedures, simulation tool, and debugging.

Assignment 2.2 One or two design projects using the micro-controller

Assignment 2.3 : Design projects that involve interrupts.

CPU Presentations.

Assignment 3 : Research project on processors (e.g., Intel Pentium) resulting in a written report and oral (powerpoint) presentation. The total duration is 4-5 weeks but much of the work is done outside of class. A lab session is for a tutorial on processors by the lab instructor, and another lab session is for the oral presentation by students.

Hardware description language (HDL) and field programmable gated arrays (FPGAs).

Assignment 4.1: Introduction to HDL (e.g., verilog) and FPGAs.

Assignment 4.2 : Design project using HDL and programming an FPGA.
There may be an Assignment 4.3 as well.

Multi-cycle CPU design and hardware implementation.

Assignment 5: Design a RISC processor (e.g., multi-cycle MIPS) using HDL. The objective is to write synthesizable code and to correctly program an FPGA.

Course Outcomes

Measure and calculate characteristics of digital circuits.
Apply micro-controllers to design problems. At least one design should include interrupts.
Design using HDL and FPGAs.
Design and implement a processor using HDL and FPGAs.
Know how to use design tools including functional simulators, logic synthesizers, and hardware description languages (e.g., VHDL and Verilog).
Research a processor and give written and oral reports about its important features.
Write clear technical reports. (The course is Writing Intensive (W).)
Know how to work in a team. (Lab assignments require group work.)

Teaching Assistant (TA) Information:

TA: Ashok Balasubramaniam. ashok@spectra.eng.hawaii.edu
Office Hours: TBA
Tel: 956-9736 (Office)

Instructions:

You must attend every lab on the scheduled days and times, and come on time. You may be excused only if you have a doctor's note with a valid reason. If you must miss a lab then contact the T.A. Ashok (email or telephone) before the Lab.
Each individual is required to submit their own individual lab report except for Assignment 3 Computer Reports, which requires a group report. Lab reports will be collected at the beginning of the session, unless notified otherwise. No late reports will be accepted. Note that this laboratory satisfies the writing intensive (WI) requirement. Therefore, the reports will be graded on writing style. Each report must follow the format explained here. The following are links to additional guidelines to write good reports.
- Technical Report Writing for Engineering Students – An overview
- Report Style from the University of Edinburgh, UK
Read lab handouts before coming to labs to help insure that assignments are completed on time.
Use the computers and other equipment in the Laboratory for the intended experiments and not for personal use.
Do not damage any kind of laboratory equipment. You can be held responsible.
Follow the Lab Safety Rules for your own security!!!

Grading Policy

Grading is based on lab reports and demonstrations, i.e., presentations to the TA that the assignment was carried out partially or to completion. Each assignment is graded as follows:

Writing Style of Lab Report (50%). Each assignment requires a lab report. Fifty percent of the grade is based upon the writing style of the reports. All lab reports should be written well and follow the format but they will be graded differently. The following are the three grading styles:
- Grading With Revision. Reports are graded/commented for writing style. Students may then revise the reports and turn them in again for a final grade. Therefore, there are two due-dates for the report, where the second due-date is for the revision.
- Grading Without Revision. In this case, there is only one due-date and there are no revisions.
- Loose Grading. Reports are graded less strictly than for normal grading but the report still must be clear, include all necessary information, and be free of spelling and grammatical mistakes.
Demonstration (50%). The TA will judge whether the assignment was partially or fully completed by
- In-lab demonstrations by students (e.g., showing a circuit works propertly)
- Reading the lab reports, which means the reports must be clear, complete, and organized
- In the case of Assignment 3 "CPU Reports", the demonstration is the oral presentation, which should be done using powerpoint slides.
Demonstrations count 50%.

Grades are based on the standard curve, i.e., 90% = A, 80% = B, 70% = C, 60% = D, and below 60% is an F.

Textbook and Reading Assignments

We have a textbook for the lab course, Advanced Digital Design with Verilog HDL by M. Ceiletti Prentice-Hall. It covers design methods for the Verilog Hardware Description Language (HDL) and field programmable gated arrays (FPGAs). This will be useful for Lab Assignments 4.1, 4.2, and 5

List of Assignments

0. Introduction
- Date and Points: 8/26 [1 week, 0 pts]
- Lab Report: None.
- Read instructions to write lab reports. All lab reports must conform to the format.
1. Measurement of TTL characteristics
- Date and Points: 9/2 [1 week, 10 pts]
- Lab Report:
2.1. Micro-Controllers: Introduction to the PIC 16F84A
- Date and Points: 9/9 [1 week, 10 pts]
- Lab Report
- More Information
2.2. Micro-Controllers: Traffic Light Controller
- Date and Points: 9/16 [1 week, 10 pts]
- Lab Report
2.3. Micro-Controllers: Interrupts and Simulation in MPLAB
- Date and Points: 9/23 [1 week, 10 pts]
- Lab Report
3. CPU Presentations
- Date and Points: TBA [4 weeks, 30 pts]
- TA will give an overview of CPUs during a lab session (TBA)
- Lab Report
- Oral Presentation
4.1. Verilog HDL and FGPAs: Part I (The assignment is under construction. It will cover introduction to FPGAs, FPGA design tools such as Xilinx Webpack 5.2, XSA 100 development board, proper Verilog HDL design and functional simulation and testing.)
- Date and Points: TBA [3 lab sessions (Oct. 7, 14, and 21), 10 pts] The sessions will be held during the same period as Lab Assignment 3 CPU Presentations.
- Lab Report
- Reading Assignment: Ciletti, For the first lab session read Chap 1 and 8. Optional reading is Chap 2. For the second lab session read Chapter 4.
4.2. Verilog HDL and FGPAs: Part II (The assignment is under construction. It will cover synthesis and post synthesis design tasks.)
- Date and Points: TBA [2 lab sessions, 10 pts] The sessions will be held during the same period as Lab Assignment 5 Final Project.
- Lab Report
- Reading Assignment: Ciletti. For the first lab session read parts of Chap 6, and for the second lab session read parts of Chap 11.
5. Final Project: Multi-Cycle CPU Design and Implementation

Date and Points: TBA [4 Weeks, 40 pts]
Lab Report

Grading Style: Grading Without Revision
Due date: TBA