EE 361 Homework 10
Due Date
December 5, 2003 (fri), at the beginning of class. There
will be no extensions (since we need time to grade before the end of the
semester)!
Assignment
[This homework assignment is worth 20 points]
You are to design a single-cycle MIPS processor using Verilog
HDL, and the Veriwell simulator. The processor is the same MIPS processor
we have discussed in class and is presented in the textbook. A block
diagram of the processor is shown in Figure 5.29 of the textbook on page
372.
Your MIPS processor has to execute the following instructions:
- R-type instructions add, sub, and, or, and slt
- lw and sw
- beq
- addi
- j
Your MIPS module must have the following format.
module
Mips(pcout,aluresult,clk,reset,pminstr);
output [31:0] pcout; // Program counter value
output [31:0] aluresult; // Output of the alu. used for debugging
input clk;
// Clock signal.
input reset; //
Reset to clear the program counter (PC).
// if reset = 1 then PC = 0 at the next positive clock
edge
// if reset = 0 then PC works as normal, i.e., it
// parallel loads at the next positive
clock edge.
input [31:0] instr; // Instruction from instruction memory
.
.
.
endmodule
Note that your Data Memory should have at least 16 memory cells at memory
locations 0, 4, 8, ....
Instructions
The instructions will consist of a number of steps.
Step 1, Building Components of the MIPS computer that's on page 372,
Figure 5.29. Try to get this done by November 7.
Build the following modules in verilog (test bench each module to verify
it works)
- 2:1 multiplexer -- example given in lecture notes
- register file -- example given in lecture notes
- ALU -- example given in lecture notes
- PC -- simple
- Data Memory -- similar to register file
- Control -- just a ROM
- ALU Control -- just a ROM
Note that the following can all be implemented with continuous assigns
(one continuous assign per operation) You may
skip testbenching since they're pretty short. But if you're unsure,
then test bench.
- shift left 2
- add (such as for incrementing the pc by 4)
- sign extend
- and gate
We'll work on program memory in later steps.
Step 2, Do the following Project A: This project
checks if your processor can execute R-type instructions. Label this project
HW10A.PRJ. It should have
- Your MIPS processor (you create this)
- The testbench hw10Main.V, which you can download here.
- The instruction memory hw10IM1.V, which you can download here. This program has R-type instructions.
The program in the instruction memory assumes that the register file is
initiailized to
$3 = 23
$4 = 24
$5 = 25
$6 = 26
$12 = 1
$13 = 3
$14 = 8
You can initialize the registers by adding the following into your register
file module
initial
begin
RegCell[3]=23;
RegCell[4]=24;
RegCell[5]=25;
RegCell[6]=26;
RegCell[12]=1;
RegCell[13]=3;
RegCell[14]=8;
end
As an example, you can download my register file by clicking here. The initial procedure is at the bottom of the
register file module.
Create a Windows folder and it should have the label "LastNameFirstInitial
EE 361 Hw 10". For example, if your name is John Doe then the folder's
name will be "DoeJ EE 361 Hw 10". Put your files in the folder.
This may take a little longer than a week. Get it down by Nov. 17
(monday).
Here are some suggestions (pdf file) to accomplish
the project.
Step 3, Do the following Project B: This project
checks if your processor can execute lw, sw, and beq instructions. Label this
project HW10B.PRJ. It should have
- Your MIPS processor.
- The testbench hw10Main.V (same one).
- The instruction memory hw10IM2.V, which you can download here. This program has lw, sw, and beq instructions.
It loops around a few times, while reading and writing to memory.
Put this project and its files in your Windows folder.
This should take about a week, so expect to finish Nov. 24.
Last Step, Do the following Project C: This project
checks if your processor can execute addi and j instructions. Label this
project HW10C.PRJ. It should have
- Your MIPS processor.
- The testbench hw10Main.V (same one).
- The instruction memory hw10Test3.V, which you can download here. This program loops around a few times and includes
the addi and j instructions.
Put this project and its files in your Windows folder.
How to Turn In
Make sure the projects HW10A.PRJ, HW10B.PRJ, and HW10C.PRJ and verilog files,
including your processor and instruction memories are in your windows folder.
In the folder, also include a README file that is either a text ( .txt)
or Word (.doc) file. The file should contain on separate lines
- "Homework 10, EE 361, Fall 2003"
- Date
- List of projects that work, and where you can find them (if
they're in folders). Not that you will get partial credit for the projects
that do work.
Compress the Windows folder as a zip file. Then email the zipped file
to the grade Jason Ebisu at ebisu@wiliki.eng.hawaii.edu by 1230pm on the due
date December 5. In the email, the subject heading should be "EE 361
Hw 10". Also, cc the file to the instructor at sasaki@spectra.eng.hawaii.edu,
and to yourself for your record.