EE 361 Fall 2002 Lecture Outline

Overview

• I. Instruction Set Architecture (and Assembly Language): (Approximately 4 weeks). Sub-topics to be covered
  • Instructions that a computer can execute.
  • Assembly language
  • Compiling, and other related operating system software.
  • Data representation
  • Subroutines and Stacks
  • Exceptions (interrupts)
• II. MIPs Processor Design: (Approximately 3.5 weeks). Sub-topics to be covered
  • Review of digital circuit parts and design techniques.
    • Parts: registers, register files, RAM, combinational circuits, sequential circuits (Mealy machines), multiplexers, demultiplexers, and tri-states.
    • Design Techniques: modular design, ASM charts, state diagrams, design procedure from state diagrams or ASM charts to sequential circuits.
    • Verilog HDL -- structural Verilog.
  • Single-Cycle MIPS Processor
  • Multi-Cycle MIPS Processor
  • Performance: critical paths, propagation delays, set-up times, holding times.
• III. Processor Component Design: (3.5 weeks).
  • ALU: implementing integer arithmetic, iterative partitioning in space and time, multiplication, division, and Booth's algorithm.
  • Controller: design techniques such as one-hot encoding and microprogramming.
  • Performance.
• IV. Other Important Stuff: (2 weeks).
  • Memory Hierarchy: caching, virtual memory.
  • Floating point

Instruction Set Architecture - Assembly Language

A.

• Introduction. [Aug. 26]
  • Reading: Textbook-- Chap. 2 and in particular Secs. 2.1-2.3, 2.5-2.7. [Optional: Read Chap. 1 and the rest of Chap. 2.]. Notes-- A.1-A.8.
• Instructions and operands. [Aug. 28]
  • Reading: Textbook-- Sec. 3.1-3.3. Notes-- A.9-A.22.
• Instruction format, assembly and branching/jumping. [Aug. 30]
  • Reading: Textbook-- Sec. 3.4-3.5. Notes-- A.22-A.39.

B.

• Subroutines and stacks. [Sept. 4]
  • Reading: Sec. 3.6. Notes -- A.36-A.38, B.1-B.4
• Addressing modes, immediate addressing, PC-relative adressing. [Sept. 6, 9]
  • Reading: Sec. 3.7 (this section is about text characters, which will be discussed later in the course), 3.8. Notes -- B.5-B.17
• Passing parameters through registers and stack. [Sept. 9, 11]
  • Reading: Sec. 3.9, 3.10, and A.1. Notes -- B.17-B.33.

C.

• The way to do procedure calls in MIPs, stack frames, some details about the MIPs assembly language. [Sept. 13, 16]
  • Reading: Sec. A.2, A.5, and A.6. Notes -- C.1-C.9.
• Big picture: assemblers, linkers, and loaders. [Sept. 16, 18]
  • Reading: Sec. A.3, A.4. Notes -- C.10-C.16.
• Mopping up: arrays versus pointers, properties and rules of thumb, CISC. [Sept. 25]
  • Reading: Secs. 3.11, 3.12 (optional), 3.13 (optional). Notes -- C.17-C.21.

D.

• Positional number systems, addition, conversion from binary to octal and hex, unsigned integers. [We haven't covered this yet]
  • Reading: Sec. 4.1-4.2.
• Signed numbers, twos complement, negation, addition [We haven't covered this yet]
  • Reading: Sec. 4.3.
• Exceptions [Sept. 20, 23]
  • Reading: Sec. 5.6. but from page 410 to the middle of page 413.

MIPS Processor Design

E. Review of Digital Circuit Design and Verilog. No reading assignments except ones given in homeworks.

• Review of Basic Parts: combinational circuits, truth tables, logic operations, and Verilog HDL and modules. [Sept. 25, 27]
• More Basic Parts and their implementation with verilog: multiplexers, demultiplexers, registers, register files, and tri-states. [Sept. 30]
• Midterm Exam 1 [Oct. 2]
• Overview of FPGAs [Oct. 4]
• Sequential Circuits, Mealy machines, ASM charts, and state diagrams. [Oct. 7]

F. Single-Cycle MIPS Processor

• Overview of datapath [Oct. 9]
  • Reading: Sec. 5.1-5.2.
• Complete overview of datapath [Oct. 11]
  • Reading: Sec. 5.3.
• Single cycle architecture: control [Oct. 14]
  • Reading:

G.Multi-Cycle MIPS Processor

• A multiple clock cycle implementation. [Oct. 25]
  • Reading: Sec. 5.4.
• A multiple clock cycle implementation -- datapath. [Oct. 28]
  • Reading: Sec. 5.4.
• A multiple clock cycle implementation -- state diagram of controller. [Oct. 30]
  • Reading:

H. Controller Design [Nov. 1, fri]

• Controller design -- One-hot encoding
• Microprogramming.
  • Reading: Sec. 5.5. and App. C.
• Microprogramming -- implementation of controller. [Nov. 8, fri]
  • Reading:

Processor Component Design

I. ALU Design

• Logic operations (AND, OR, Compl., XOR), simple ALU by iterative partitioning in space. [Nov. 18]
  • Reading: Sec. 4.4.
• Carry-lookahead and carry-save, shifting, barrel shifter, cross-bar switch. [Nov. 20]
  • Reading: Sec. 4.5.

J. ALU Design

• Three versions of unsigned multiplying. Booth's algorithm for signed multiply. [Nov. 25]
  • Reading: Sec. 4.6.
• Division. [Nov. 27]
  • Reading: Sec. 4.7.

Other Important Stuff

K. Floating Point

• Floating point definitions and hardware [12/2]
  • Reading: Sec. 4.8.

L. Memory Hierarchy

• RAM -- dynamic and static [12/4]
  • Reading: Sec. 7.1-7.2, and handouts
• Caches [12/6]
  • Reading:
• Virtual Memory [12/9]
  • Reading: Sec. 7.3.
• Common framework for memory hierarchies (we won't get to this)
  • Optional Reading: Sec. 7.4.