EE 361L -- Fall 2002

Under Construction. Last Update: 8/22/03

Objectives

EE 361L is the laboratory course for EE 361 Digital Systems and Computer Design. You will study computers and computer circuit design. The lab is composed of five sets of assignments.

1. Measurement of TTL Characteristics. You will measure current and voltages on the inputs and outputs of digital circuits, and then determine physical limitations of putting circuits together.
2. Micro-Controllers. There are three assignments to introduce micro-controllers, which are one-chip computers used for controlling systems, e.g., automobile engines, appliances, etc. They are relatively small and cheap digital circuits that are capable of complex control.
- You will use micro-controllers in circuit designs. In this way, you will see how computers are used as circuits.
- You will learn Input/Output (I/O) concepts including interrupts.
- You will see how software interacts with hardware.
- You will use the PIC micro-controller 16F84A and its support tools, such as the simulator and compiler.
3. Computer Reports. You will research a computer to understand its organization and how it works. You will present your findings in written and oral reports.
- You will practice technical research and self-studying technical information.
- You will practice your communication skills in explaining technical material.
- By attending presentations of other groups, you will get an overview of many processors.
4. Verilog HDL and FPGAs. Hardware description languages (HDL) and field programmable gated arrays (FPGAs) are powerful tools for computer circuit designers. HDLs resemble high-level programming languages but are used to specify digital circuits. The most popular HDLs are Verilog and VHDL. We will use Verilog, which resembles the C programming language.
FPGAs are digital circuits on a chip that can be programmed (configured) and re-programmed. Due to their flexibility, they are used to quickly design and implement systems.
- You will write Verilog code that is synthesizable, i.e., code that can be translated into hardware.
- You will implement your Verilog code into FPGA circuits.
- You will check timing and understanding how proper design can improve performance (speed).
5. Multi-Cycle Processor Implementation. The final project is to design and implement a processor using synthesizable Verilog code. The processor will be a variation of the MIPS processor discussed in EE 361.

The lab is Writing Intensive. Therefore, lab reports will be graded for writing style, which will count towards around 50% of the overall grade. Good communication skills are important for any successful engineer.

Teaching Assistant (TA) Information:

TA: Ramesh Kandula
Email: ramesh@spectra.eng.hawaii.edu
Office Hours: Mon and Thur 9-11am H488
Tel: 956-9736 (Office)

Instructions:

You must attend every lab on the scheduled days and times, and to come on time. You may be excused only if you have a doctor's note with a valid explanation. If you have a valid reason to miss a lab then contact the T.A. Ramesh Kandula (email or telephone) before the Lab.
Each individual is required to submit their own individual lab report except for Assignment 3 Computer Reports, which requires a group report. Lab reports will be collected at the beginning of the session, unless notified otherwise. No late reports will be accepted. Note that this laboratory satisfies the writing intensive (WI) requirement. Therefore, the reports will be graded on writing style. Each report must follow the format explained here. The following are links for additional guidelines to write good reports.
- Technical Report Writing for Engineering Students – An overview
- Report Style from the University of Edinburgh, UK
Read lab handouts before coming to labs to help insure that assignments are completed on time.
Use the computers and other equipment in the Laboratory for the intended experiments and not for personal use.
Do not damage any kind of laboratory equipment. You can be held responsible.
Follow the Lab Safety Rules for your own security!!!

Grading Policy

Grading is based on lab reports and demonstrations, i.e., showing to the TA that the assignment was carried out partially or to completion. Each assignment is graded as follows:

Writing Style of Lab Report (50%). Note that each assignment requires a lab report. Fifty percent of the grade is based upon the writing style of the reports. All lab reports should be written well and follow the format but they will be graded differently. The following are the three grading styles:
- Normal Grading. Reports are for their writing style.
- Loose Grading. Reports are graded less strictly than for normal grading but the report still must be clear, include all necessary information, and be free of spelling and grammatical mistakes.
- Normal Grading With Revision. This is like Normal Grading except you will have an opportunity to revise and resubmit your report after receiving comments and corrections.
Demonstration (50%). The TA will judge whether the assignment was partially or fully completed by
- In-lab demonstrations from students (e.g., showing a circuit works propertly)
- Reading the lab reports, which means the reports must be clear, complete, and organized
- In the case of Assignment 3 "CPU Reports", the demonstration is the oral report.
Demonstrations count 50%.

Grades are based on the standard curve, i.e., 90% = A, 80% = B, 70% = C, 60% = D, and below 60% is an F.

List of Assignments

0. Introduction [0 pts] Date: 8/27
- No report.
- Read instructions to write lab reports. All lab reports must conform to the format.
1. Measurement of TTL characteristics [1 Week, 10 pts] Date: 9/3
- Report Grading Style: Normal Grading With Revision. Submit report on 9/10. Your report will be corrected and returned 9/17. Then you may revise and resubmit your report on 9/24.
2.1. Micro-Controllers: Introduction to the PIC 16F84A [1 Week, 10 pts] Date: 9/10
- Report Grading Style: Loose Grading. Submit report on 9/17.
- More Information
2.2. Micro-Controllers: Traffic Light Controller [1 Week, 10 pts] Date: 9/17
- Report Grading Style: Normal Grading. Submit report on 9/24.
2.3. Micro-Controllers: Interrupts and Simulation in MPLAB [1 Week, 10 pts] Date: 9/24
- Report Grading Style: Normal Grading With Revision. Submit report on 10/1. Your report will be corrected and returned 10/8. Then you may revise and resubmit your report on 10/15.
3. CPU Presentations [4 Weeks, 30 pts] Date: 10/1
- Report Grading Style: Normal Grading With Revision. Submit report around 10/29, though the exact submission dates will be given later.
4.1. Verilog HDL and FGPAs: Part I [1 Week, 10 pts] Date: 10/8
- Report Grading Style: Loose Grading. Submit report on 10/15.
4.2. Verilog HDL and FGPAs: Part II [1 Week, 10 pts] Date: 10/15
- Report Grading Style: Loose Grading. Submit report on 10/22.
5. Final Project: Multi-Cycle CPU Design and Implementation [4 Weeks, 40 pts] Date: 12/9 (demos) and 12/13 (everything else)
- Report Grading Style: Normal Grading. Submission dates of written report, verilog code, and floppy disk will be 12/13 (fri) 3pm but the demos are due 12/9, the last lab.