EE 361 Fall 2001 Lecture Outline

Overview

I. Instruction Set Architecture (and Assembly Language): (Approximately 4 weeks). Sub-topics to be covered

II. MIPs Processor Design: (Approximately 3.5 weeks). Sub-topics to be covered

Review of digital circuit parts and design techniques.
- Parts: registers, register files, RAM, combinational circuits, sequential circuits (Mealy machines), multiplexers, demultiplexers, and tri-states.
- Design Techniques: modular design, ASM charts, state diagrams, design procedure from state diagrams or ASM charts to sequential circuits.
- Verilog HDL -- structural Verilog.
Single-Cycle MIPS Processor
Multi-Cycle MIPS Processor
Performance: critical paths, propagation delays, set-up times, holding times.

III. Processor Component Design: (3.5 weeks).

ALU: implementing integer arithmetic, iterative partitioning in space and time, multiplication, division, and Booth's algorithm.
Controller: design techniques such as one-hot encoding and microprogramming.
Performance.

IV. Other Important Stuff: (2 weeks).

Introduction. (8/27)
- Reading: Textbook-- Chap. 2 and in particular Secs. 2.1-2.3, 2.5-2.7. [Optional: Read Chap. 1 and the rest of Chap. 2.]. Notes-- A.1-A.8.
Instructions and operands. (8/29)
- Reading: Textbook-- Sec. 3.1-3.3. Notes-- A.9-A.22.
Instruction format, assembly and branching/jumping. (9/5)
- Reading: Textbook-- Sec. 3.4-3.5. Notes-- A.22-A.39.

Subroutines and stacks. (9/10)
- Reading: Sec. 3.6. Notes -- A.36-A.38, B.1-B.4
Addressing modes, immediate addressing, PC-relative adressing. (9/12)
- Reading: Sec. 3.7 (this section is about text characters, which will be discussed later in the course), 3.8. Notes -- B.5-B.17
Passing parameters through registers and stack. (9/15)
- Reading: Sec. 3.9, 3.10, and A.1. Notes -- B.17-B.33.

The way to do procedure calls in MIPs, stack frames, some details about the MIPs assembly language. (9/17)
- Reading: Sec. A.2, A.5, and A.6. Notes -- C.1-C.9.
Big picture: assemblers, linkers, and loaders. (9/19)
- Reading: Sec. A.3, A.4. Notes -- C.10-C.16.
Mopping up: arrays versus pointers, properties and rules of thumb, CISC. (9/21)
- Reading: Secs. 3.11, 3.12 (optional), 3.13 (optional). Notes -- C.17-C.21.

Positional number systems, addition, conversion from binary to octal and hex, unsigned integers. (9/24)
- Reading: Sec. 4.1-4.2.
Signed numbers, twos complement, negation, addition (9/26)
- Reading: Sec. 4.3.
Exceptions (10/9)
- Reading: Sec. 5.6. but from page 410 to the middle of page 413.

E. Review of Digital Circuit Design and Verilog. No reading assignments except ones given in homeworks.

Review of Basic Parts: combinational circuits, truth tables, logic operations, and Verilog HDL and modules. (9/28)
More Basic Parts and their implementation with verilog: multiplexers, demultiplexers, registers, register files, and tri-states. (10/1)
Exam (10/3)
No class (10/5)
Sequential Circuits, Mealy machines, ASM charts, and state diagrams. (10/8)

F. Single-Cycle MIPS Processor

G.Multi-Cycle MIPS Processor

A multiple clock cycle implementation.
- Reading: Sec. 5.4. (10/22)
A multiple clock cycle implementation -- datapath.
- Reading: Sec. 5.4. (10/24)
A multiple clock cycle implementation (10/26) -- state diagram of controller.
- Reading:

H. Controller Design

I. ALU Design

Logic operations (AND, OR, Compl., XOR), simple ALU by iterative partitioning in space. (10/31)
- Reading: Sec. 4.4.
Carry-lookahead and carry-save. (11/5,11/7)
- Reading: Sec. 4.5.
Shifting, barrel shifter, cross-bar switch. (11/7)
- Reading: Notes

Everything below the line is under construction

J. ALU Design

K. Floating Point

L. Memory Hierarchy