EE 361 Homework 8

• November 16, 2001 (friday)

Assignment: (20 pts)

You are to design a single-cycle MIPS processor using Verilog HDL, and the Veriwell simulator. Turn in your code on a diskette. Your code should include a test sequence, which will be given to you in class. The processor is the same MIPS processor we have discussed in class and is presented in the textbook. A block diagram of the processor is shown in Figure 5.29 of the textbook on page 372.

To simplify the design, your MIPS processor only has to execute the following instructions:

• R-type instructions add, sub, and, or, and slt
• lw and sw
• beq
• addi
• j

The following are benefits of doing the assignment:

• Learning a little about Verilog HDL, which is widely used in industry for designing computer circuits.
• Experience with designing a moderately large system. Employers like this type of experience especially if you can grasp the importance of modular design.
• A better understanding of the MIPS processor (and procesors in general) by trying to make one work.

Turn in your verilog implementation of the MIPS at the beginning of class, November 16, friday.

• Put your Verilog code into proper format as follows:
  • Have a Veriwell Project that runs the first test program. Call this project HW8A.PRJ.
  • Have a Veriwell Project that runs the second test program. Call this project HW8B.PRJ.
  • Have a Veriwell Project that runs the third test program. Call this project HW8C.PRJ.
  • Each of these projects should have the main module as described above. This means that you should have a module labeled "Mips" that models the MIPS computer - without the instruction memory (which is another module). The module should have the following first few lines

    module Mips(pcout, instr, aluresult, clk);
    
    output  [31:0] pcout;     // Output from program counter inside Mips module
    input   [31:0] instr;     // Input from program (or instruction) memory.  It's
                              //    the instruction to be executed
    output  [31:0] aluresult; // Output result of the ALU
    input   clk;              // Clock signal 
    
    

• Write instructions on how to run your Veriwell Projects. Be clear.
• Turn in your disk and instructions Nov. 16 at the beginning of class.