EE 260 Lecture Schedule
Spring 2008
GALEN SASAKI
University of Hawaii
SUBJECT TO CHANGES!
Last Update December 12, 2007
The textbook has been updated so the reading assignments may change
and the dates for the lectures may change too.
The main objectives for EE 260 are for the students to
 be able to design and build smalltomoderate sized circuits
 understand modular design
 be able to understand large complicated circuits
 have some understanding of how the topics of EE 260, EE 211,
and EE 160 are related.
The remainder of this page has an outline of the organization of the course, and a description
of each lecture.
 Introduction
to Sequential Circuit Design. (Approx. seventeen lectures.)
 Topics
 Graphical descriptions of sequential
 State diagrams
 ASM charts
 Implementation of sequential circuits
 The Mealy machine
 Examples of state registers: D flip flop, T
flip flop, JK flip flop.
 Examples of combinational circuit technology: PROMs,
NANDs, NORs, XORs, ANDs, ORs, voltage inverters.
 Design techniques
 Kmaps
 Boolean algebra and logic, multilevel circuits
 Mixed logic
 Translation from ASM chart (or state diagram) to
circuit
 Timing
 Propagation delay of combinational circuits,
critical path
 Timing for sequential circuits: set up time,
holding time, propagation delay
 Example: traffic light controller
 Objective: you should be able to design and build
small to moderate sized circuits.
 From
Switches to Combinational Circuits. (approx. four lectures.)
 Topics
 Basic electronics
 Ohms law
 Pull up and pull down resistors
 MOSFETs
 Normally open and normally closed switches
 Implementation of combinational circuits using normally
open and normally closed switches.
 NAND, NOR, and voltage inverters
 Tristates, transmission gates, opencollector NAND
(also cover the "wiredand")
 PALs, and PROMs.
 Multiplexers and Demultiplexers and review of techniques
 Objective: Understand how combinational circuits
can be constructed from very elementary circuits. You should also get
some understanding of the connection between EE 211 and EE 260.
 Modular
Design. (approx. nine lectures.)
 Topics
 Modular design techniques
 Functional partitioning
 Iterative partitioning
 Hierarchical partitioning
 Common MSI parts
 Multiplexers and demultiplexers
 As a combinational circuits
 Implementation using iterative partitioning and
hierarchical partitioning.
 Ripple adders: implementation using iterative
partitioning
 Shift registers and counters: implementation using
iterative partitioning
 Iterative partitioning in time
 RAM
 Example: Keyboard controller (learn about ASCII and
parallel to serial conversion)
 Objective: you should be familiar with commonly used
circuit parts, and should be able to break down a design problem into
one of designing a network of smaller modules.
 Computer.
(approx. nine lectures.)
 Topics
 Signed integer representation: sign magnitude, ones
complement, twos complement
 Octal, hex representation
 Overall computer organization: CPU, memory, I/O
 Programming a computer
 I/O hardware
 Internal design of a CPU
 Objective: Understanding how a microprocessor (a large
circuit) works, and how hardware is related to software.
 Important
Details. (approx. three lectures.)
 Topics
 Building sequential circuits from combinational ones
 Latches, clocked latches, flip flops
 Characteristic functions
 Clock skews
 Multiphase clocks and masterslave flip flops
 Glitches (unwanted signals), how to avoid them
 Objective: understand how sequential circuits can be
built from combinational circuits, and get more exposure to possible
circuit problems
PART 1
Introduction to Sequential Circuit Design
Lecture 1: [1 day ]
 Topics:
 Course overview
 Objectives of course
 Syllabus
 What's expected of students
 Basic definitions
 Digital and analog circuits
 Combinational circuits
 Sequential circuits
 Clock signal
 Mealy machine
 Lecture Notes: A.1A.8.
 Reading Assignment: Textbook: Sections 1.11.2 (pp.
19).
Lecture 2: [1 day ]
 Topics:
 Positional number systems
 Decimal number example
 radix or base
 Binary numbers
 Powers of two
 Conversion from binary to decimal
 Conversion from decimal to binary
 Why does conversion from decimal to binary work?
 Addition
 Example of decimal addition  concept of carry
 Binary addition
 Listing binary numbers: (fact 1) nbit binary numbers can be
written from (n1)bit binary numbers, (fact 2) there are 2**n nbit
binary numbers. (Here, "2**n" represents "2" to the power "n".)
 Lecture Notes: A.9A.16.
 Reading Assignment:
 Textbook: Read Section 1.3 (pp. 915).
 Read Sections A.1  A.3.1 (pp. 511517). This reading will
also cover octal
and hexadecimal numbers which we will cover in later
lectures.
Lecture 3: [ 1 day ]
 Topics:
 An example design of a sequential circuit
 Outline of design procedure
 Hot tub controller example + a solution
 State diagram description of the solution
 Description of a state diagram
 Mealy machine
 State register implementation with D flip flop +
definition of a D flip flop
 Definition the combinational circuit for the Mealy
machine + state transition table
 Let's see how the circuit will work
 Lecture Notes:A.17A.27.
 Reading Assignment: Textbook: Read Section 1.4
(pp. 1520).
 Presentations: HotTub.ppt
Powerpoint presentation that shows timing diagram of hot tub
controller.
Lecture 4: [1 day]
 Topics:
 Review of hot tub controller
 Outline of design procedure
 Specification of what our Mealy machine should do
 Implementing the state register  description of 74175, GND,
VCC, and CLR.
 Implementing the combinational circuit
 Definition of a PROM (Programmable Read Only Memory).
 2716  an available PROM (actually it's often referred
to as an EPROM, for Erasable PROM).
 Making a PROM from a larger (taller and wider) one.
Introduce the "don't care" concept.
 Final circuit implementation of hot tub controller.
 Lecture Notes: B.1B.8
 Reading Assignment:
 Read the beginning of Section 1.3.4 (on page 21) until page
22 (up until but not including the "Schematic Rules of Composition").
 Read Sec. 1.4 (pp. 1520)
 Presentations: ROM.pdf, pdf
document of the ROM presentation.
Lecture 5: [ 1 day ]
 Topics:
 Review hot tub controller design. Show that don't cares can
be used in state transition tables and truth tables.
 Directional lights design example
 Lecture Notes: B.9B.16
 Reading Assignment: Section 1.4 continued (pp. 2025)
Lecture 6: [2 days]
 Topics:
 ASM charts and how they're similar to state diagrams
 ASM chart of hot tub controller
 Go over again the components of ASM chart
 Examples of going from ASM chart to state transition table
 How to draw nice ASM charts
 Examples of bad ASM charts
 Lecture Notes: B.17B.24
 Reading Assignment: You will be reading parts of Chapter 7
"Finite State Machine Design". Finite state machines (FSMs) are
machines (or circuits) that have a finite number of states (obviously).
In particular, all the sequential digital circuits covered
in this course are FSMs. This chapter will sometimes reference a
"counter" circuit which we will cover later in the course.
 Read Introduction to Chap 7 (pp. 307308).
 Read part of Section 7.1 (pp. 308311) but stop before
"NextState Logic". This will give you an introduction to
counters and some terms used in sequential circuit design (e.g., "state
table"). Don't worry about understanding the circuits shown in
Figures 7.17.2. The section refers to BCD and gray code whose
definitions can be found on page 55 and page 71, respectively.
 Read part of Section 7.3 (pp. 327  330) but stop before
"Implementation". This gives a summary of how to design a
sequential circuit. We will discuss techniques for implementation
later.
 Read Sections 7.3.2 and 7.3.3 (pp. 332334) on Mealy and
Moore circuits
 Read Section C.1 (566568) on flip flops. Flip flops
are often used as state registers for Mealy and Moore circuits. Three
often used flip flops (T, D, and JK) are shown
in the figure below along with their state diagrams.
Figure. The T, D, and JK flip flops.
Lecture 7: [1 day]
 Topics:
 Example design where outputs depend on inputs as well as the
state
 Solution in words
 State diagram representation of the solution
 ASM chart representation of the solution  introduce output
boxes
 Rules to draw ASM charts
 Example of converting ASM chart to state diagram
 Lecture Notes: C.1C.8
 Reading Assignment:
 Continue with the earlier reading assignment if you have not
finished.
 Presentations: Moore.pdf
Lecture 8: [1 day]
 Topics:
 Logic functions  alternative to truth tables
 Boolean expressions
 Basic components
 Basic operators + logic symbols
 Composing functions
 Associative and commutative laws
 Logic Diagrams
 Examples of logic diagram and evaluation of logic functions
 Lecture Notes: C.9C.16
 Textbook Reading Assignment:
 Read Section 2.1 (pp. 3337).
 Read Section 2.2 up through the axions of boolean logic
Section 2.2.1 (pp. 3841)
Lecture 9: [1 day]
 Topics
 Review boolean expressions
 Expressions without parentheses
 Conversion from boolean expressions to circuit diagrams
 NAND
 Wire device
 Voltage inverter
 Lecture Notes: C.17C.24
 Reading Assignment:
 Read Section 2.3 (pp. 4652)
Lecture 10: [1 day]
 Topics:
 Example design problem
 Design procedure
 Procedure to convert truth table to combinational circuit
 Sum of Products (SOP) expression
 Logic diagram
 Introduction to mixed logic  matching bubbles
 Lecture Notes: D.1D.8
 Reading Assignments:
 Section 2.3.4 (pp. 5256)
Lecture 11: [1 day]
 Topics:
 Mixed Logic introduction
 Steps to convert a logic diagram to a circuit diagram.
 Another example of conversion
 Finding minimum SOPs (MSOPs)  Kmaps, gray code
 Implicants represent product terms
 Lecture Notes: D.9D.16
 Reading Assignment:
 Section 2.4 (pp. 5658) Don't read page 39 or beyond.
 Presentations: KMap.pdf
Lecture 12: [1 day]
 Topics:
 Finding MSOPs  review Kmap concepts
 Construct a boolean expression from implicants
 A covering
 Overlap is okay
 Prime implicants (the bigger the better)  how to find them
 Essential prime implicants
 Steps to go from truth table to MSOP
 Example
 Lecture Notes: D.17D.24
 Reading Assignment: Section 2.5 (pp. 6569)
Lecture 13: [ 1 day ]
 Topics:
 Example combinational circuit design problem
 Review of steps to find MSOPs
 2 and 3 variable Kmaps
 Logic diagram of example
 NOR circuit
 circuit diagram
 5 variable Kmap
 Bool  computer method
 Lecture Notes: E.1E.8
 Reading Assignment: Section 2.5 (pp. 6972).
Lecture 14: [1 day]
 Topics:
 Boolean algebra laws
 Duality
 Factoring and what it means to circuits
 De Morgan's Theorem
 Product of sums (POS) + De Morgan's theorem and the
relationship between POS and SOP expressions.
 Canonical POS expressions
 What about don't cares?
 Minimized POS.
 Lecture Notes: E.9E.16
 Reading Assignment: There's a bunch of stuff to read
here, but there will be no textbook reading assignments for Lectures
1517
 Read Section 2.5 (pp. 7276)
 Read Section 2.2 (pp. 3741)
Lecture 15: [ 1 day ]
 Topics: The traffic light controller example
 Design Problem
 Modular approach  different modules and their functions
 ASM chart for the controller
 Lecture Notes: E.17E.24
 Reading Assignment:
Section 2.2 (pp. 4246)
 Presentation: Building D flip flops
Lecture 16: [ 1 day ]
 Topics:
 Design of the timer module
 Continuation of the Traffic Light Controller
 Use JK, T, and D flip flops as a state register 
Excitation tables
 Use a counter as a state register
 Design of the button module
 Reading Assignment: Section 2.6 (pp. 7680)
 Lecture Notes: F.1F.8
Lecture 17: [ 2 days ]
 Topics:
 Continuation of the Traffic Light Controller
 ASM chart of controller
 Design of controller  using flip flops
 Design of display module
 Timing
 An example circuit  How fast can it run?
 Flip flop timing: set up, holding time, prop delay
 Prop delay of the combinational circuit  critical path
 Example calculation
 Reading Assignment: Complete reading Section 2.4
from pp. 5965.
 Lecture Notes: F.9F.17
PART 2
From Switches to Combinational Circuits
Lecture 18: [ 2 days ]
 Topics:
 Logic by switches
 Normally open and normally closed switches
 Implementing logic functions  complementary logic
 ORing means switches in parallel, ANDing means
switches in series
 Using DeMorgan's theorem
 Example
 FET realization of switches
 Basic electricity
 Description of pmos and nmos FETs
 CMOS implementations of inverters, NANDs, and NORs
 Lecture Notes: F.18F.24
 Reading Assignment: Optional read Section B.1 (pp.
553536) and Section. B.4.1B.4.3 (pp. 543547)
Lecture 19: [2 days]
 Topics:
 Review of switching theory
 Tristates and Transmission gates
 XOR circuit
 What're the XOR, AND, and OR circuits good for?
 Voltage divider, and pullup and pulldown resistors
 ANDing and ORing with switches and pullup and pulldown
resistors
 Opencollector NAND and Wire'd AND
 Lecture Notes: G.1G.8
 Reading Assignment: The reading assignment describes
what's in a typica data sheet for a circuit such the data sheet that
was handed out to you in Lab.
 Read Section B.5, pp. 554556, "Elements of the Data Sheet"
Lecture 20: [ 2 days ]
 Topics:
 Programmable array of logic gates
 PLAs
 Implementing PLAs using switches
 Example PLA layout
 PALs
 Comparison between PALs and PLAs
 Example PAL layout
 Registered PAL
 Lecture Notes: G.9G.16
 Reading Assignment: The beginning of Section
4.1, pp. 155161
Lecture 21: [ 1 day ]
 Topics:
 Short description of multiplexers and demultiplexers
 Multiplexer definition
 Example applications
 As a combinational circuit
 Various ways to implement a multiplexer
 Demultiplexer definition
 Example applications
 Various ways to implement a demultiplexer

 Lecture Notes: G.17G.24
 Reading Assignment: Part of Section 4.2, pp
171179. If you are limited on time you may skip the examples.
PART 3
Modular Design
Lecture 22: [ 1 day ]
 Topics:
 Different partitioning techniques: functional, hierarchical,
iterative
 Comparator design example by iterative partitioning
 Comparator design by hierarchical partitioning
 Ripple adder
 Half adder and full adder
 A iterative partitioning example for the class to do
 Lecture Notes: H.1H.8
 Reading Assignment:
 Read Section 5.6, pp. 238239 "Half Adder/Full Adder"
Lecture 23: [ 1 day ]
 Topics:
 Review of hierarchical partitioning
 Hierarchical implementation of multiplexer
 Hierarchical implementation of demultiplexer
 Review of iterative partitioning
 Implementation of universal shift register
 Description of register
 Implementation
 Alternative design of the module
 Lecture Notes: H.9H.16
 Reading Assignment: For the next few lectures, we'll
be covering counters and shift registers.
 Read Section 6.3, pp. 289293. But don't read Example 6.3
Lecture 24: [ 1 day ]
 Topics:
 Implementation of the 74163 4bit upcounter
 Description
 Implementation
 Iterative partitioning in time  basic idea of ripple adder
 Lecture Notes: H.17H.24
 Reading Assignments: Read the beginning of Section
7, pp. 307317 but skip Examples 7.2, 7.3, and 7.5.
Lecture 25:
 Topics:
 Overview of adder and what it should do
 Handshaking
 Datapath of adder
 ASM chart of the controller
 Implementation of the controller using a counter and decoder
 Lecture Notes: I.1I.8
 Reading Assignments: Read Examples 7.2 and 7.3 (pp.
312316)
Lecture 26: [Mar 28, mon]
 Topics:
 Memory modules
 ROM and registers
 Organization of addressable memory: CS, Enable, address
decoding, output enable, and tristates
 Register file
 Building a taller ROM from shorter ones
 RAM  memory module
 Applications
 Reading from RAM
 Lecture Notes: I.9I.16
 Reading Assignment: Section 10.4.1, pp. 467470.
Lecture 27: [Mar 30, wed]
 Topics:
 Review of what was covered about RAM
 Writing to RAM
 Review of memory access of RAM
 Building larger RAMs from smaller ones
 Memory unit with a mix of RAM and ROM
 Buses
 Example datapath with buses
 Lecture Notes: I.7I.24
 Reading Assignment: No textbook reading assignments
Lectures 28 and 29 [We already did this]
 Topics: Keyboard controller
 Lecture Notes: J notes
PART 4
Computer
Lectures 30 and 31: [Apr 1 and 4]
 Topics:
 Representation of signed integers
 Sign magnitude
 1s complement
 2s complement
 Arithmetic
 Conversion from decimal to 2s complement
 Overflow
 Octal and Hexadecimal numbers
 Lecture Notes: K.1K.16
 Reading assignment: .Section A.4, pp. 520529.
Lecture 32: [Dates will be announced but it'll basically be 12 days
per lecture number]
 Topics:
 Basic computer architecture
 Memory
 CPU
 Accountant example
 More specifics about EE 260 computer  how all the pieces
are connected, the DT signal, the R/W* signal, address bus, and data
bus.
 Types of registers in our CPU: general purpose regs. A and B,
and PC
 Lecture Notes: L.1L.8
 Reading Assignment: There are no reading assignments
for the basic computer, which runs over multiple lectures. There
is a long reading assignment for Lectures 3941, so get started on
that. Much of it is review of material we covered earlier
this semester.
Lecture 33:
 Topics:
 Review of computer
 How it executes instructions
 Memory organization
 Instruction types
 Data transfer instruction examples
 Data manipulation examples
 Program control examples
 Lecture Notes: L.9L.16
 Reading Assignment: None
Lecture 34:
 Topics:
 Review computer  memory organization and registers in CPU
 Review instructions from last lecture
 Example program
 Hardware in memory
 Instruction format  How programs are stored in memory,
opcodes, absolute and immediate addressing modes
 Complete list of instructions
 Machine code for example program
 Lecture Notes: L.17L.26
 Reading Assignment: None
Lecture 35:
 Topics:
 Directional lamps problem  IO problem
 Basic idea of memory mapped IO  registers and tristates are
made to look like memory cells.
 Address decoding circuitry for IO
 Basic idea of software driver for this example
 Two program fragments for the driver
 The entire program
 The machine code for the program
 Lecture Notes: M.1M.10
 Reading Assignment: None
Lecture 36:
 Topics:
 Design of the CPU  datapath and controller (IR)
 Components of the datapath
 Registers and tristates
 ALU

 Datapath showing registers, ALU, tristates, and the topbus
and downbus
 One tick of the datapath  selection configuration of the
topbus, ALU, and downbus. How the controller selects these using
demultiplexers.
 Hardware for the DT and R/W* signals
 Lecture Notes: M.11M.18
 Reading Assignment: None
Lecture 37:
 Topics:
 Review of datapath and what happens in a tick
 ASM chart of controller + von Neumann processing cycle
 Example of how to accomplish a memory transfer
 Microoperations of first three ticks  fetch opcode byte and
update PC, register transfer notation
 TAB instructions, noop operation
 LDIA and LDA instruction
 SUBIA and STA instruction
 JMP instruction
 Lecture Notes: M.19M.26
 Reading Assignment: None
Lecture 38:
 Topics:
 Review what the controller should do
 Single instruction controller
 Controller that does not do conditional jumps
 Full blown controller
 Reset pin
 Lecture Notes: M.27M.34
 Reading Assignment: None
PART 5
Important Details
Lecture 39:
 Topics:
 Example sequential circuit with two transmission gates and
two inverters
 RS latch
 Analysis of RS latch
 Characteristic equation of RS latch
 Application to debounding a switch
 Lecture Notes: N.1N.8
 Reading Assignment: Section 6.1 (pp. 261278)
. This is long so it will be continued for Lecture 40
Lecture 40:
 Topics:
 Types of memory elements: flip flops, latches, level
sensitive latches (or clocked latches).
 D, T, JK, and RS flip flops and their characteristic
functions
 D, T, JK, and RS latches
 D, T, JK, and RS level sensitive latches
 Summary
 Implementation of negative edge triggered D flip flop from
clocked latches
 Lecture Notes: N.9N.16
 Reading Assignment: Continuation of Lecture 39
reading assignment.
Lecture 41:
 Topics:
 Masterslave JK flip flop
 Clock skews and multiphase clocks
 Glitches and hazards
 Glitches and hazards due to propagation delay
 How to fix them
 Lecture Notes: N.17N.24
 Reading Assignment: Section 6.2 (pp. 278284) and
stop before reading Section 6.2.4.