EE 260 Lecture Schedule
Spring 2004

GALEN SASAKI
University of Hawaii

SUBJECT TO CHANGES!
Last Update 3/12/04

The main objectives for EE 260 are for the students to

1. be able to design and build small-to-moderate sized circuits
2. understand modular design
3. be able to understand large complicated circuits
4. have some understanding of how the topics of EE 260, EE 211, and EE 160 are related.

The remainder of this page has an outline of the organization of the course, and a description of each lecture.

ORGANIZATION

1. Introduction to Sequential Circuit Design. (Approx. seventeen lectures.)
   • Topics
     • Graphical descriptions of sequential
       • State diagrams
       • ASM charts
     • Implementation of sequential circuits
       • The Mealy machine
       • Examples of state registers: D flip flop, T flip flop, JK flip flop.
       • Examples of combinational circuit technology: PROMs, NANDs, NORs, XORs, ANDs, ORs, voltage inverters.
       • Design techniques
         • K-maps
         • Boolean algebra and logic, multilevel circuits
         • Mixed logic
         • Translation from ASM chart (or state diagram) to circuit
       • Timing
         • Propagation delay of combinational circuits, critical path
         • Timing for sequential circuits: set up time, holding time, propagation delay
       • Example: traffic light controller
   • Objective: you should be able to design and build small to moderate sized circuits.
2. From Switches to Combinational Circuits. (approx. four lectures.)
   • Topics
     • Basic electronics
       • Ohms law
       • Pull up and pull down resistors
       • MOSFETs
       • Normally open and normally closed switches
     • Implementation of combinational circuits using normally open and normally closed switches.
       • NAND, NOR, and voltage inverters
       • Tri-states, transmission gates, open-collector NAND (also cover the "wired-and")
       • PALs, and PROMs.
     • Multiplexers and Demultiplexers and review of techniques
   • Objective: Understand how combinational circuits can be constructed from very elementary circuits. You should also get some understanding of the connection between EE 211 and EE 260.
3. Modular Design. (approx. nine lectures.)
   • Topics
     • Modular design techniques
       • Functional partitioning
       • Iterative partitioning
       • Hierarchical partitioning
     • Common MSI parts
       • Multiplexers and demultiplexers
         • As a combinational circuits
         • Implementation using iterative partitioning and hierarchical partitioning.
       • Ripple adders: implementation using iterative partitioning
       • Shift registers and counters: implementation using iterative partitioning
       • Iterative partitioning in time
       • RAM
     • Example: Keyboard controller (learn about ASCII and parallel to serial conversion)
   • Objective: you should be familiar with commonly used circuit parts, and should be able to break down a design problem into one of designing a network of smaller modules.
4. Computer. (approx. nine lectures.)
   • Topics
     • Signed integer representation: sign magnitude, ones complement, twos complement
     • Octal, hex representation
     • Overall computer organization: CPU, memory, I/O
     • Programming a computer
     • I/O hardware
     • Internal design of a CPU
   • Objective: Understanding how a microprocessor (a large circuit) works, and how hardware is related to software.
5. Important Details. (approx. three lectures.)
   • Topics
     • Building sequential circuits from combinational ones
       • Latches, clocked latches, flip flops
       • Characteristic functions
       • Clock skews
       • Multiphase clocks and master-slave flip flops
     • Glitches (unwanted signals), how to avoid them
   • Objective: understand how sequential circuits can be built from combinational circuits, and get more exposure to possible circuit problems

LECTURES

PART 1
Introduction to Sequential Circuit Design

Lecture 1: [Jan. 12, mon]

• Topics:
  • Course overview
    • Objectives of course
    • Syllabus
    • What's expected of students
  • Basic definitions
    • Digital and analog circuits
    • Combinational circuits
    • Sequential circuits
    • Clock signal
    • Mealy machine
• Lecture Notes: A.1--A.8.
• Reading Assignment: Textbook pp. 1-11, stopping at Section 1.2.2.

• Topics:
  • Positional number systems
    • Decimal number example
    • radix or base
  • Binary numbers
    • Powers of two
    • Conversion from binary to decimal
    • Conversion from decimal to binary
    • Why does conversion from decimal to binary work?
  • Addition
    • Example of decimal addition -- concept of carry
    • Binary addition
  • Listing binary numbers: (fact 1) n-bit binary numbers can be written from (n-1)-bit binary numbers, (fact 2) there are 2**n n-bit binary numbers. (Here, "2**n" represents "2" to the power "n".)
• Lecture Notes: A.9-A.16.
• Reading Assignment:
  • Continue reading the textbook from page 11 and stop at page 16 (before Sec. 1.3).
  • Read pp. 650-657. This reading will also cover octal and hexadecimal numbers which we will cover in later lectures.

• Topics:
  • An example design of a sequential circuit
    • Outline of design procedure
    • Hot tub controller example + a solution
    • State diagram description of the solution
    • Description of a state diagram
    • Mealy machine
    • State register implementation with D flip flop + definition of a D flip flop
    • Definition the combinational circuit for the Mealy machine + state transition table
    • Let's see how the circuit will work
• Lecture Notes:A.17-A.27.
• Reading Assignment: Continue reading the textbook from page 16, and stop at page 21 (before Sec. 1.3.4 on Gates).
• Presentations:  HotTub.ppt  Powerpoint presentation that shows timing diagram of hot tub controller.
  

• Topics:
  • Review of hot tub controller
    • Outline of design procedure
    • Specification of what our Mealy machine should do
  • Implementing the state register -- description of 74175, GND, VCC, and CLR.
  • Implementing the combinational circuit
    • Definition of a PROM (Programmable Read Only Memory).
    • 2716 -- an available PROM (actually it's often referred to as an EPROM, for Erasable PROM).
    • Making a PROM from a larger (taller and wider) one. Introduce the "don't care" concept.
  • Final circuit implementation of hot tub controller.
• Lecture Notes: B.1-B.8
• Reading Assignment:
  • Read the beginning of Section 1.3.4 (on page 21) until page 22 (up until but not including the "Schematic Rules of Composition").
  • Read Sec. 1.3.5, pages 24-27.
  • Presentations:  ROM.pdf,  pdf document of the ROM presentation.
    

• Topics:
  • Review hot tub controller design. Show that don't cares can be used in state transition tables and truth tables.
  • Directional lights design example
• Lecture Notes: B.9-B.16
• Reading Assignment: Section 1.4 on page 31-35.

• Topics:
  • ASM charts and how they're similar to state diagrams
  • ASM chart of hot tub controller
  • Go over again the components of ASM chart
  • Examples of going from ASM chart to state transition table
  • How to draw nice ASM charts
  • Examples of bad ASM charts
• Lecture Notes: B.17-B.24
• Reading Assignment: You will be reading parts of Chapter 8 "Finite State Machine Design". Finite state machines (FSMs) are machines (or circuits) that have a finite number of states (obviously). In particular, all the sequential digital circuits we'll be looking at in this course are FSMs. This chapter will sometimes reference a "counter" circuit. A counter circuit is a certain type of sequential circuit. We'll be covering counter circuits later in the course.
  • Read pp. 383-384. Note that after page 384, there is a discussion on "Implementation", but skip this because this is ahead of our lecture.
  • Read Section 8.2.1 (which starts on page 388) up until but not including the "Implementation", which starts at the bottom of page 391. In this section there is a reference to sequential circuits called flip flops. Flip flops are often used as state registers for the Mealy machine. Three often used flip flops (T, D, and JK) are shown in the figure below along with their state diagrams. Also note that Step 6 in page 389 makes reference to "Boolean equations", "K-maps", etc. These are implementation methods we will be covering later.
  • Read Section 8.2.2 (starting at page 389) up until but not including the "Implementation" at the bottom of page 391.

Figure. The T, D, and JK flip flops.

• Topics:
  • Example design where outputs depend on inputs as well as the state
  • Solution in words
  • State diagram representation of the solution
  • ASM chart representation of the solution -- introduce output boxes
  • Rules to draw ASM charts
  • Example of converting ASM chart to state diagram
• Lecture Notes: C.1-C.8
• Reading Assignment: You will be reading parts of Section 8.3 "Alternative State Machine Representations". This section covers Algorithmic State Machine (ASM) notation and Hardware Description Languages (HDL). ASM notation (or ASM charts) are similar to state diagrams and are used to describe the behavior of a sequential circuit. HDL is a language (similar to pascal or C) that is also used to describe the behavior of a circuit (see page 399 for an example HDL description of a circuit). We won't be covering HDL in this course, but it is covered in more advanced courses such as EE 466.
  • Read Section 8.3.1, pp. 395-398. The ASM chart discussed in here assumes that before each variable is a prefix "L." or "H.". This indicates "positive" or "negative logic", which we'll cover in Lecture 9. For this class, we will not use this prefix, so that our diagrams are simpler. Also note that condition boxes in the textbook are hexagonal, while the condition boxes covered in lecture (and the ones we'll be using) are diamond shaped.
  • Presentations:  Moore.pdf
    

• Topics:
  • Logic functions -- alternative to truth tables
  • Boolean expressions
    • Basic components
    • Basic operators + logic symbols
    • Composing functions
    • Associative and commutative laws
    • Logic Diagrams
  • Examples of logic diagram and evaluation of logic functions
• Lecture Notes: C.9-C.16
• Textbook Reading Assignment: For the next few lectures, we'll cover material in Chapter 2.
  • Read Section 2.1, pp. 40-43. This material makes reference to a device called a "switch". We won't be covering this in lecture until much later. The definition of a switch is given Section 1.3.1 (pp. 16-18).
  • In Section 2.1.2 there is a discussion of different types of "logic gates". These are NAND, NOR, XOR, NXOR, and Implication gates. Only read the paragraph on XOR/XNOR gates in page 46.

• Topics
  • Review boolean expressions
  • Expressions without parentheses
  • Conversion from boolean expressions to circuit diagrams
  • NAND
  • Wire device
  • Voltage inverter
• Lecture Notes: C.17-C.24
• Reading Assignment: For the next two lectures, read Section 2.5 on "Practical Matters" For this lecture, read Section 2.5.1, pp. 92-96.

• Topics:
  • Example design problem
  • Design procedure
  • Procedure to convert truth table to combinational circuit
  • Sum of Products (SOP) expression
  • Logic diagram
  • Introduction to mixed logic -- matching bubbles
• Lecture Notes: D.1-D.8
• Reading Assignments:
  • Continue reading Section 2.5 on "Practical Matters." In particular, read Section 2.5.3 "Schematic Documentation Standards" (pp. 96-101) but skip the part about "Polarization and Bubbles" (pp. 98-100).
  • Read the first two pages of Section 2.2.2 "Two-Level Logic Canonical Forms", pp. 56-57. Only read the "Sum of Products" subsection. This gives the definitions of canonical form, sum-of-products (SOP) form, minterms, and the shorthand notation of SOP expression given at the top of page 57. There is a reference to DeMorgan's theorem which will be covered later. There is also a reference to a product-of-sums (POS) form which we will also cover later.

• Topics:
  • Mixed Logic introduction
  • Steps to convert a logic diagram to a circuit diagram.
  • Another example of conversion
  • Finding minimum SOPs (MSOPs) -- K-maps, gray code
  • Implicants represent product terms
• Lecture Notes: D.9-D.16
• Reading Assignment:
  • Read 2.3.3, pp. 70-75.
  • Presentations:  KMap.pdf
    

• Topics:
  • Finding MSOPs -- review K-map concepts
  • Construct a boolean expression from implicants
    • A covering
    • Overlap is okay
  • Prime implicants (the bigger the better) -- how to find them
  • Essential prime implicants
  • Steps to go from truth table to MSOP
  • Example
• Lecture Notes: D.17-D.24
• Reading Assignment: Section 2.3.5, pp. 80-83.

• Topics:
  • Example combinational circuit design problem
  • Review of steps to find MSOPs
  • 2 and 3 variable K-maps
  • Logic diagram of example
  • NOR circuit
  • circuit diagram
  • 5 variable K-map
  • Bool -- computer method
• Lecture Notes: E.1-E.8
• Reading Assignment: Section 2.3.6, pp. 83-85. Optional reading is the Quine-McCluskey Method, Section 2.4.1 pp. 85-89.

• Topics:
  • Boolean algebra laws
  • Duality
  • Factoring and what it means to circuits
  • De Morgan's Theorem
  • Product of sums (POS) + De Morgan's theorem and the relationship between POS and SOP expressions.
  • Canonical POS expressions
  • What about don't cares?
  • Minimized POS.
• Lecture Notes: E.9-E.16
• Reading Assignment: There's a bunch of stuff to read here, but there will be no textbook reading assignments for Lectures 15-17
  • Read Section 2.2.1, pp. 50-56. "Laws and Theorems of Boolean Alg"
  • Read Section 2.2.2, pp. 56-61. "Two-Level Logic Canonical Forms"
  • Read Section 2.2.4, pp. 64-65. "Incomplete Specified Functions"
  • Read Section 2.3.4, pp. 75-80. "Design". This is an example of design.
  • Read Introduction of Chapter 3 "Multilevel Combinational Logic" pp. 110-111.
  • Read pages 111 and 112 of Section 3.1 "Multilevel Logic" (don't read sec. 3.1.1)
  • Read Section 3.3.2, pp. 123-128. This section is on factoring/multilevel logic.
  • Read Section 3.5.3, pp. 151-152 "Inputs and Outputs with Switches with LEDs" Switches will be used in Lecture 16.

• Topics: The traffic light controller example
  • Design Problem
  • Modular approach -- different modules and their functions
  • ASM chart for the controller
• Lecture Notes: E.17-E.24
• Presentation:  Building D flip flops
  

• Topics:
  • Design of the timer module
    • Continuation of the Traffic Light Controller
    • Use JK, T, and D flip flops as a state register -- Excitation tables
    • Use a counter as a state register
  • Design of the button module
• Lecture Notes: F.1-F.8

• Topics:
  • Continuation of the Traffic Light Controller
    • ASM chart of controller
    • Design of controller -- using flip flops
    • Design of display module
  • Timing
    • An example circuit -- How fast can it run?
    • Flip flop timing: set up, holding time, prop delay
    • Prop delay of the combinational circuit -- critical path
    • Example calculation
• Lecture Notes: F.9-F.17

PART 2
From Switches to Combinational Circuits

• Topics:
  • Logic by switches
    • Normally open and normally closed switches
    • Implementing logic functions -- complementary logic
      • ORing means switches in parallel, ANDing means switches in series
      • Using DeMorgan's theorem
    • Example
  • FET realization of switches
    • Basic electricity
    • Description of pmos and nmos FETs
    • CMOS implementations of inverters, NANDs, and NORs
• Lecture Notes: F.18-F.24
• Reading Assignment: Read Appendix B, pp. 664-680, but skipping the following parts:
  • Skip the "Capacitance" subsection on page 667
  • Skip the "RC Delay" subsection on page 667
  • Skip Subsection B.2.2, "Diode Logic", pp. 669-670.
  • Skip Section B.3 "Bipolar Transistor Logic", pp. 671-675.
  A total of around 10 pages.

• Topics:
  • Review of switching theory
  • Tri-states and Transmission gates
  • XOR circuit
  • What're the XOR, AND, and OR circuits good for?
  • Voltage divider, and pull-up and pull-down resistors
  • ANDing and ORing with switches and pull-up and pull-down resistors
  • Open-collector NAND and Wire'd AND
• Lecture Notes: G.1-G.8
• Reading Assignment: The reading assignment describes what's in a typica data sheet for a circuit such the data sheet that was handed out to you in Lab.
  • Read Section 3.5.1, pp. 147-149, "Elements of the Data Sheet"

• Topics:
  • Programmable array of logic gates
  • PLAs
  • Implementing PLAs using switches
  • Example PLA layout
  • PALs
  • Comparison between PALs and PLAs
  • Example PAL layout
  • Registered PAL
• Lecture Notes: G.9-G.16
• Reading Assignment: We will begin reading Chapter 4 starting at page 160 and continuing through Section 4.1 (pp. 161-173) on "Programmable Arrays of Logic Gates".

• Topics:
  • Short description of multiplexers and demultiplexers
  • Multiplexer definition
  • Example applications
  • As a combinational circuit
  • Various ways to implement a multiplexer
  • Demultiplexer definition
  • Example applications
  • Various ways to implement a demultiplexer
  • 
    
• Lecture Notes: G.17-G.24
• Reading Assignment:
  • Read Section 4.2.2, pp. 181-187 "Multiplexers/Selectors"
  • Read Section 4.2.3, pp. 187-194 "Decoder/Demultiplexer"
  • Read Section 4.2.5, pp. 202-207 "Read-Only Memories"
  • Optional: Read Section 4.2.4, pp. 194-202 "Tri-state Versus Open-Collector Gates"

PART 3
Modular Design

• Topics:
  • Different partitioning techniques: functional, hierarchical, iterative
  • Comparator design example by iterative partitioning
  • Comparator design by hierarchical partitioning
  • Ripple adder
  • Half adder and full adder
  • A iterative partitioning example for the class to do
• Lecture Notes: H.1-H.8
• Reading Assignment:
  • Read Section 5.2.1, pp. 249-251 "Half Adder/Full Adder"
  • Optional: Read some examples of design in Chapter 4. In particular read Section 4.3 starting from the beginning at page 207, and finishing page 220 (don't continue through "Multilevel Optimization Method"). Notice that there is a reference to expresso which is a software tool similar to our bool program. You can also read Section 4.6, pp. 222-224, which gives a design using a multiplexer.

• Topics:
  • Review of hierarchical partitioning
  • Hierarchical implementation of multiplexer
  • Hierarchical implementation of demultiplexer
  • Review of iterative partitioning
  • Implementation of universal shift register
    • Description of register
    • Implementation
    • Alternative design of the module
• Lecture Notes: H.9-H.16
• Reading Assignment: For the next few lectures, we'll be covering counters and shift registers.
  • Read Section 7.1, pp. 327-337. "Kinds of Registers and Counters"

• Topics:
  • Implementation of the 74163 4-bit up-counter
    • Description
    • Implementation
  • Iterative partitioning in time -- basic idea of ripple adder
• Lecture Notes: H.17-H.24
• Reading Assignments:
  • Read Section 7.3, pp. 343-345. "Self-Starting Counters"
  • Optional: Section 7.2 will be review.
  • Optional: Section 7.4 will be review, except there is a reference to RS flip flops which we haven't covered yet. So skip Section 7.4.1.

• Topics:
  • Overview of adder and what it should do
  • Handshaking
  • Datapath of adder
  • ASM chart of the controller
  • Implementation of the controller using a counter and decoder
• Lecture Notes: I.1-I.8
• Reading Assignments:
  • Read Section 7.5, pp. 342-356. "Asynchronous Versus Synchronous Counters" This material will not be covered in the lectures too much, but it is good practical information.

• Topics:
  • Memory modules
  • ROM and registers
  • Organization of addressable memory: CS, Enable, address decoding, output enable, and tri-states
  • Register file
  • Building a taller ROM from shorter ones
  • RAM -- memory module
  • Applications
  • Reading from RAM
• Lecture Notes: I.9-I.16
• Reading Assignment:
  • Read Section 7.6.1, pp. 356-360, "RAM Basics: A 1024 by Four-bit Static RAM"
  • Read Section 7.6.4, pp. 364-367, "Detailed SRAM Timing"

• Topics:
  • Review of what was covered about RAM
  • Writing to RAM
  • Review of memory access of RAM
  • Building larger RAMs from smaller ones
  • Memory unit with a mix of RAM and ROM
  • Buses
  • Example datapath with buses
• Lecture Notes: I.7-I.24
• Reading Assignment: No textbook reading assignments

• Topics: Keyboard controller
• Lecture Notes: J notes

PART 4
Computer

• Topics:
  • Representation of signed integers
    • Sign magnitude
    • 1s complement
    • 2s complement
    • Arithmetic
    • Conversion from decimal to 2s complement
    • Overflow
  • Octal and Hexadecimal numbers
• Lecture Notes: K.1-K.16
• Reading assignment: Section 5.1 of Chapter 5, pp. 240-248.

• Topics:
  • Basic computer architecture
  • Memory
  • CPU
  • Accountant example
  • More specifics about EE 260 computer -- how all the pieces are connected, the DT signal, the R/W* signal, address bus, and data bus.
  • Types of registers in our CPU: general purpose regs. A and B, and PC
• Lecture Notes: L.1-L.8
• Reading Assignment: No textbook reading assignments

• Topics:
  • Review of computer
  • How it executes instructions
  • Memory organization
  • Instruction types
  • Data transfer instruction examples
  • Data manipulation examples
  • Program control examples
• Lecture Notes: L.9-L.16
• Reading Assignment: No textbook reading assignments

• Topics:
  • Review computer -- memory organization and registers in CPU
  • Review instructions from last lecture
  • Example program
  • Hardware in memory
  • Instruction format -- How programs are stored in memory, opcodes, absolute and immediate addressing modes
  • Complete list of instructions
  • Machine code for example program
• Lecture Notes: L.17-L.26
• Reading Assignment: No textbook reading assignments

• Topics:
  • Directional lamps problem -- IO problem
  • Basic idea of memory mapped IO -- registers and tristates are made to look like memory cells.
  • Address decoding circuitry for IO
  • Basic idea of software driver for this example
  • Two program fragments for the driver
  • The entire program
  • The machine code for the program
• Lecture Notes: M.1-M.10
• Reading Assignment: No textbook reading assignments

• Topics:
  • Design of the CPU -- datapath and controller (IR)
  • Components of the datapath
    • Registers and tri-states
    • ALU
    • 
      
  • Datapath showing registers, ALU, tri-states, and the top-bus and down-bus
  • One tick of the datapath -- selection configuration of the top-bus, ALU, and down-bus. How the controller selects these using demultiplexers.
  • Hardware for the DT and R/W* signals
• Lecture Notes: M.11-M.18
• Reading Assignment: No textbook reading assignments

• Topics:
  • Review of datapath and what happens in a tick
  • ASM chart of controller + von Neumann processing cycle
  • Example of how to accomplish a memory transfer
  • Microoperations of first three ticks -- fetch opcode byte and update PC, register transfer notation
  • TAB instructions, noop operation
  • LDIA and LDA instruction
  • SUBIA and STA instruction
  • JMP instruction
• Lecture Notes: M.19-M.26
• Reading Assignment: No textbook reading assignments

• Topics:
  • Review what the controller should do
  • Single instruction controller
  • Controller that does not do conditional jumps
  • Full blown controller
  • Reset pin
• Lecture Notes: M.27-M.34
• Reading Assignment: No textbook reading assignments

PART 5
Important Details

Lecture 39:

• Topics:
  • Example sequential circuit with two transmission gates and two inverters
  • RS latch
  • Analysis of RS latch
  • Characteristic equation of RS latch
  • Application to debounding a switch
• Lecture Notes: N.1-N.8
• Reading Assignment:
  • Section 6.1.1, pp. 284-288 "Simple Circuits With Feedback"
  • Section 6.1.2, pp. 288-292 "State, Clock, Setup, and Holding Time"
  • Section 6.1.3, pp. 292-293 "The R-S Latch"
  • Section 6.1.4, pp. 293-294 "The J-K Flip Flop" but for now skip the discussion on the master-slave flip flop.
  • Section 6.6.1, page 317 "Debouncing Switches"

• Topics:
  • Types of memory elements: flip flops, latches, level sensitive latches (or clocked latches).
  • D, T, JK, and RS flip flops and their characteristic functions
  • D, T, JK, and RS latches
  • D, T, JK, and RS level sensitive latches
  • Summary
  • Implementation of negative edge triggered D flip flop from clocked latches
• Lecture Notes: N.9-N.16
• Reading Assignment:
  • Read Section 6.2, pp. 299-306 "Timing Methodologies"

• Topics:
  • Master-slave JK flip flop
  • Clock skews and multi-phase clocks
  • Glitches and hazards
  • Glitches and hazards due to propagation delay
  • How to fix them
• Lecture Notes: N.17-N.24
• Reading Assignment:
  • Finish Reading Section 6.1.4, pp. 293-295, "J-K Flip Flops"
  • Read the beginning of Section 6.1.5 (first three paragraphs), pp. 295-296, "Edge-Triggered Flip-Flops: D Flip-Flops, T Flip-Flops"
  • Read Section 3.4, pp. 141-147 "Hazards/Glitches and How to Avoid Them"