EE 361 Homework 8A

Problem 1 [8 pts]

You will build the MIPS-L0 processor in verilog.  A description of the MIPS-L0 processor can be found in the Hardware Design Tips  notes as follows.  Go to the EE 361 web site -->  Lecture schedule and notes --> Lecture notes --> Hardware Design Tips.

The MIPS-L0 is a simplified version of  the MIPS-L, which is a 16 bit version of the single cycle MIPS.  You will build the MIPS-L in an upcoming assignment.

Your MIPS-L0 module should look like this.

module MipsL0(iaddr,aluout,aluina,aluinb,clock,reset,idata);
output [15:0] iaddr;                  // Program counter value.
output [15:0] aluout,aluina,aluinb;   // Output of the ALU used for debugging.
input clock;     
input reset;                    // Reset to clear PC.  If reset = 1 then next clock transition
                                //     will clear PC.      
input [15:0] idata;             // Where the instruction is input from the program memory

.
.
.
endmodule

Instructions

• Register file RegFileL0:  has registers $0-$7.  Registers $0, $4, and $5 are stuck at the values, respectively, 0, 2, and 1.
  
• ALU:  Description can be found in notes
  
• ALU Control:  A ROM
• PC unit:  Check if it can be reset and incremented properly
  

• Your MIPS-L0 processor (you create this)
• The testbench for the MIPS-LO which you can download here. [This test bench should work but let me know if it doesn't]
  
• The instruction memory to be used with the testbench which you can download here.  This memory module has been verified using the following testbench:  testbenchIM.V